HWA
Bare metal programming with style
adx_2.h
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1 
2 /* This file is part of the HWA project.
3  * Copyright (c) 2012,2015 Christophe Duparquet.
4  * All rights reserved. Read LICENSE.TXT for details.
5  */
6 
13 #define _hw_adxclock_ioclk , _hw_adxckdiv, 1.0
14 #define _hw_adxclock_min , _hw_adxckmin, 1.0
15 #define _hw_adxclock_max , _hw_adxckmax, 1.0
16 
17 
18 HW_INLINE uint8_t _hw_adxckdiv( float v )
19 {
20  if ( v == 1.0 / 128 ) return 7 ;
21  if ( v == 1.0 / 64 ) return 6 ;
22  if ( v == 1.0 / 32 ) return 5 ;
23  if ( v == 1.0 / 16 ) return 4 ;
24  if ( v == 1.0 / 8 ) return 3 ;
25  if ( v == 1.0 / 4 ) return 2 ;
26  if ( v == 1.0 / 2 ) return 1 ;
27 
28  HWA_E(HW_EM_AVL(clock,(ioclk/2**(1..7))));
29 
30  return 0 ;
31 }
32 
33 
34 HW_INLINE uint8_t _hw_adxckmin( float v __attribute__((unused)) )
35 {
36  if ( HW_SYSHZ / 128 >= 50000 ) return 7 ;
37  if ( HW_SYSHZ / 64 >= 50000 ) return 6 ;
38  if ( HW_SYSHZ / 32 >= 50000 ) return 5 ;
39  if ( HW_SYSHZ / 16 >= 50000 ) return 4 ;
40  if ( HW_SYSHZ / 8 >= 50000 ) return 3 ;
41  if ( HW_SYSHZ / 4 >= 50000 ) return 2 ;
42  return 1 ;
43 }
44 
45 
46 HW_INLINE uint8_t _hw_adxckmax( float v __attribute__((unused)) )
47 {
48  if ( HW_SYSHZ / 2 < 200000 ) return 1 ;
49  if ( HW_SYSHZ / 4 < 200000 ) return 2 ;
50  if ( HW_SYSHZ / 8 < 200000 ) return 3 ;
51  if ( HW_SYSHZ / 16 < 200000 ) return 4 ;
52  if ( HW_SYSHZ / 32 >= 50000 ) return 5 ;
53  if ( HW_SYSHZ / 64 >= 50000 ) return 6 ;
54  return 7 ;
55 }
56 
57 
58 /* Enable / disable
59  */
60 #define _hw_enable_adx_(o,a,...) _hw_write(o,en,1) HW_EOL(__VA_ARGS__)
61 #define _hwa_enable_adx_(o,a,...) _hwa_write(o,en,1) HW_EOL(__VA_ARGS__)
62 
63 #define _hw_disable_adx_(o,a,...) _hw_write(o,en,0) HW_EOL(__VA_ARGS__)
64 #define _hwa_disable_adx_(o,a,...) _hwa_write(o,en,0) HW_EOL(__VA_ARGS__)
65 
66 
67 /* Start a conversion
68  */
69 #define _hw_trigger_adx_(o,a,...) _hw_write( o, sc, 1 )
70 #define _hwa_trigger_adx_(o,a,...) _hwa_write( o, sc, 1 )
71 
72 
73 /* Read the result of the conversion
74  */
75 #define _hw_rdadx_(o,a,...) _HW_B(_hw_rdadx,__VA_ARGS__)(o,__VA_ARGS__,)
76 #define _hw_rdadx1(o,...) _hw_read(o, adc)
77 #define _hw_rdadx0(o,k,...) HW_BW(_hw_rdadx0,hi8,k)(o,k,__VA_ARGS__) // `hi8` ?
78 #define _hw_rdadx01(o,k,...) (*(volatile uint8_t*)(HW_ADDRESS((o,adc))+1))
79 #define _hw_rdadx00(o,k,...) HW_BW(_hw_rdadx00,lo8,k)(o,k,__VA_ARGS__) // `lo8` ?
80 #define _hw_rdadx001(o,k,...) (*(volatile uint8_t*)(HW_ADDRESS((o,adc))))
81 #define _hw_rdadx000(o,k,...) HW_E(HW_EM_AL(k,(lo8,hi8)))
82 
83 
84 /* Read the ADC result with interrupts disabled and restore state as soon
85  * as possible.
86  */
87 #define _hw_ardadx_(o,a,...) _hw_atomic_read(o, adc)
88 
89 
90 /* Status
91  */
92 typedef union {
93  uint8_t byte ;
94  struct {
95  unsigned int __0_5 : 6 ;
96  unsigned int busy : 1 ;
97  unsigned int __7 : 1 ;
98  };
99 } _hw_adx__status_t ;
100 
101 #define _hw_stat_adx_(o,a,...) _hw_adx__status(_hw_read(o,sra)) HW_EOL(__VA_ARGS__)
102 
103 HW_INLINE _hw_adx__status_t _hw_adx__status( uint8_t byte )
104 {
105  _hw_adx__status_t st ;
106  st.byte = byte ;
107  return st ;
108 }
109 
110 
111 /*******************************************************************************
112  * *
113  * Context management *
114  * *
115  *******************************************************************************/
116 
117 #define _hwa_setup__adx_(o) \
118  _hwa_setup_r( o, admux ); \
119  _hwa_setup_r( o, sra ); \
120  _hwa_setup_r( o, srb )
121 
122 #define _hwa_init__adx_(o) \
123  _hwa_init_r( o, admux, 0x00 ); \
124  _hwa_init_r( o, sra, 0x00 ); \
125  _hwa_init_r( o, srb, 0x00 )
126 
127 #define _hwa_commit__adx_(o) \
128  _hwa_commit_r( o, admux ); \
129  _hwa_commit_r( o, sra ); \
130  _hwa_commit_r( o, srb )
HWA_E
#define HWA_E(...)
Trigger an error after code optimization.
Definition: hwa_2.h:17