Class _ctb: General-purpose 32-bit counter-timer

This class is used by:

• STM32F411: counter2, counter5

Relatives

• Interrupts
  • (COUNTER,irq): counter overflow IRQ (update event)
• Registers
  • (COUNTER,prescaler): one 16-bit prescaler
  • (COUNTER,reload): reload register (ARR)
  • Hardware registers: cr1, cr2, smcr, dier, sr, egr, ccmr1, ccmr2, ccer, cnt, psc, arr, dcr, dmar.
  • Logical registers: ckd, arpe, cms, dir, cmsdir, opm, cmsdiropm, urs, udis, cen, ti1s, mms, ccds, etp, ece, etps, etf, msm, ts, sms, tde, ude, tie, uie, ie, if
• (COUNTER,channel1..4): 4 independent channels of capture (input) or compare (output)

Interface

By default, hw( configure, COUNTER, ... ) and hwa( configure, COUNTER, ... ) configure the COUNTER as a counter:

hw | hwa( configure,      counter2,
 
        [ mode,           counter, ]                 // Default mode
 
          //  How the counter is clocked
          //
          clock,          from_apb1_psc              // See note
                        | channel1
                        | channel2
                        | external
                        | xor123,
 
          direction,      up
                        | down
                        | updown,
 
          //  The following is accepted only when direction is 'up_down'
          //
        [ compare_flag,   counting_up
                        | counting_down
                        | counting_up_or_down, ]     // Default
 
        [ prescaler,      x, ]                       // Any value in 0..0xFFFF
 
        [ reload,         x, ]                       // Any value in 0..0xFFFF
 
        [ run,            yes
                        | no ]
);

Note

RM0008, p. 126: The timer clock frequencies are automatically fixed by hardware. There are two cases:

1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.
2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected.

Note

To be implemented. Configure the counter as an encoder:

hw | hwa( configure, counter2,
 
          mode,      encoder,
 
          ...
);

Note

To be implemented. Configure the counter as a slave:

hw | hwa( configure,   counter2,
 
          mode,        slave,
 
          //  How the counter is clocked
          //
          clock,       from_apb1             // Internal clock (CK_INT)
                     | channel1
                     | channel2
                     | external
                     | encode(channel1,channel2)
                     | xor(channel1,channel2,channel3)
 
          //  How the counter is reset (slave mode)
          //
        [ reset,       counter1
                     | counter2
                     | counter3
                     | counter4
                     | counter5
                     | counter8, ]
);

hw( run, COUNTER ) and hwa( run, COUNTER ) run the counter:

hw | hwa ( run, counter2 );

hw( stop, COUNTER ) and hwa( stop, COUNTER ) stop the counter:

hw | hwa ( stop, counter2 );

hw( read, COUNTER ) returns the value of the counting register:

uint16_t v = hw( read, counter2 );

hw( write, COUNTER, value ) sets the value of the counting register:

uint16_t v = hw( write, counter2, 500 );

hw( stat, COUNTER ) gets the status flags and clears them:

uint16_t v = hw( stat, counter2 );