Class _sab: Universal Synchronous Asynchronous Receiver Transmitter

Relatives

• Registers
  • Hardware registers: sr, dr, brr, cr1, cr2, cr3, gtpr
  • Logical registers: over8, ue, m, wake, pce, ps, peie, txeie, tcie, rxneie, idleie, te, re, rwu, sbk, linen, stop, clken, cpol, cpha, lbcl, lbdie, lbdl, add, onebit, ctsie, ctse, rtse, dmat, dmar, scen, nack, hdsel, irlp, iren, eie, gt, psc
• Interrupts

Interface

• Configuration

hw|hwa( configure,      USART,
 
      [ mode,           uart, ]      // Default
      
      [ divider,        x, ]         // Value of the clock divider
      
      [ clockhz,        x,           // Source clock frequency
        bps,            y,           // Transfer rate in bits per second.
       [tol,            z,]]         // Tolerance for bps (0.01 is 1%)
 
      [ databits,       8            // Default
                      | 9, ]
 
      [ parity,         none         // Default
                      | even
                      | odd, ]
 
      [ stopbits,       1            // Default
                        0.5
                        1.5
                      | 2, ]
 
      [ cts,            on   
                      | off, ]       // Default
 
      [ rts,            on   
                      | off, ]       // Default
 
      [ receiver,       on   
                      | off, ]       // Default
 
      [ transmitter,    on
                      | off ]        // Default
 
      [ run,            yes
                      | no ] );      // Default