15 #define hw_class__nvica
17 #define hw_nvic_iser0 _r32, 0x0000, 0xFFFFFFFF, 0xFFFFFFFF
18 #define hw_nvic_iser1 _r32, 0x0004, 0xFFFFFFFF, 0xFFFFFFFF
19 #define hw_nvic_iser2 _r32, 0x0008, 0x0000FFFF, 0x0000FFFF
21 #define hw_nvic_icer0 _r32, 0x0080, 0xFFFFFFFF, 0xFFFFFFFF
22 #define hw_nvic_icer1 _r32, 0x0084, 0xFFFFFFFF, 0xFFFFFFFF
23 #define hw_nvic_icer2 _r32, 0x0088, 0x0000FFFF, 0x0000FFFF
25 #define hw_nvic_ispr0 _r32, 0x0100, 0xFFFFFFFF, 0xFFFFFFFF
26 #define hw_nvic_ispr1 _r32, 0x0104, 0xFFFFFFFF, 0xFFFFFFFF
27 #define hw_nvic_ispr2 _r32, 0x0108, 0x0000FFFF, 0x0000FFFF
29 #define hw_nvic_icpr0 _r32, 0x0180, 0xFFFFFFFF, 0xFFFFFFFF
30 #define hw_nvic_icpr1 _r32, 0x0184, 0xFFFFFFFF, 0xFFFFFFFF
31 #define hw_nvic_icpr2 _r32, 0x0188, 0x0000FFFF, 0x0000FFFF
38 #define hw__nvica_ , _hw_nvicarl
45 #define _hw_nvicarl(o1,o2,...) _hw_nvicarl1(o2,_hw_isr_##o2##_,)
46 #define _hw_nvicarl1(...) _hw_nvicarl2(__VA_ARGS__)
47 #define _hw_nvicarl2(o,x,...) HW_BW(_hw_nvicarl2,_isr,x)(o,x,__VA_ARGS__)
48 #define _hw_nvicarl20(o,...) ,(nvic,o),HW_EM_OO(nvic,o)
49 #define _hw_nvicarl21(o,c,n,isr,...) HW_B(_hw_nvicarl3,n)(o,n,__VA_ARGS__)
50 #define _hw_nvicarl31(o,n,...) ,(nvic,o),HW_EM_OO(nvic,o)
51 #define _hw_nvicarl30(o,n,...) _nvi, n
54 #if !defined __ASSEMBLER__
57 hwa_r32_t iser0, iser1, iser2 ;
58 hwa_r32_t icer0, icer1, icer2 ;
59 hwa_r32_t ispr0, ispr1, ispr2 ;
60 hwa_r32_t icpr0, icpr1, icpr2 ;
61 hwa_r32_t iabr0, iabr1, iabr2 ;
62 hwa_r32_t ipr0, ipr1, ipr2, ipr3, ipr4, ipr5, ipr6, ipr7, ipr8, ipr9 ;
63 hwa_r32_t ipr10, ipr11, ipr12, ipr13, ipr14, ipr15, ipr16, ipr17, ipr18, ipr19 ;