HWA
Bare metal programming with style
cta_2.h
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1 
2 /* This file is part of the HWA project.
3  * Copyright (c) 2017 Christophe Duparquet.
4  * All rights reserved. Read LICENSE.TXT for details.
5  */
6 
12 /* Load the channels interface definitions
13  */
14 #include "cca_2.h"
15 
64 #define hw_class__cta
65 
66 #define hw_configure__cta , _hw_cfctd
67 #define hwa_configure__cta , _hwa_cfctd
68 
69 #define _hw_cfctd(o,a,k,...) do{ HW_B(_hwx_cfctd,k)(_hw,o,k,__VA_ARGS__) }while(0)
70 #define _hwa_cfctd(o,a,k,...) do{ HW_B(_hwx_cfctd,k)(_hwa,o,k,__VA_ARGS__) }while(0)
71 
72 /* At least one keyword
73  */
74 #define _hwx_cfctd1(...) HW_E(HW_EM_AML((clock,direction)))
75 #define _hwx_cfctd0(h,o,k,...) HW_B(_hwx_cfctd_kmode,_hw_is_mode_##k)(h,o,k,__VA_ARGS__)
76 
77 /* Optionnal parameter `mode`
78  */
79 #define _hw_cfctd_mode_counter , _hwx_cfctd
80 #define _hw_cfctd_mode_encoder , HW_E_TBI
81 #define _hw_cfctd_mode_slave , HW_E_TBI
82 
83 #define _hwx_cfctd_kmode0(...) _hwx_cfctd(__VA_ARGS__)
84 #define _hwx_cfctd_kmode1(h,o,k,v,...) HW_B(_hwx_cfctd_vmode,_hw_cfctd_mode_##v)(h,o,v,__VA_ARGS__)
85 #define _hwx_cfctd_vmode1(h,o,v,...) HW_A1(_hw_cfctd_mode_##v)(h,o,__VA_ARGS__)
86 #define _hwx_cfctd_vmode0(h,o,v,...) HW_E(HW_EM_VAL(v,mode,(counter,encoder,slave)))
87 
88 /* Mode 'counter' - Mandatory parameter `clock`
89  */
90 #define _hwx_cfctd(h,o,k,...) HW_B(_hwx_cfctd_kclock,_hw_is_clock_##k)(h,o,k,__VA_ARGS__)
91 #define _hwx_cfctd_kclock0(h,o,k,...) HW_E(HW_EM_AN(k,clock))
92 #define _hwx_cfctd_kclock1(h,o,k,v,...) HW_B(_hwx_cfctd_vclock,_hw_cfctd_clock_##v)(h,o,v,__VA_ARGS__)
93 #define _hwx_cfctd_vclock0(h,o,v,...) HW_E(HW_EM_VAL(v,clock,_hw_cfctd_clocks))
94 #define _hwx_cfctd_vclock1(h,o,v,...) HW_A1(_hw_cfctd_clock_##v)(h,o,__VA_ARGS__)
95 
96 
97 #define _hw_cfctd_clocks (from_apb1_psc,ti1,ti2,xor123)
98 #define _hw_cfctd_clock_from_apb1_psc , _hwx_cfctd_clock_from_apb1_psc
99 #define _hw_cfctd_clock_ti1fed , HW_E_TBI
100 #define _hw_cfctd_clock_channel1 , _hwx_cfctd_clock_ti1fp1
101 #define _hw_cfctd_clock_channel2 , _hwx_cfctd_clock_ti2fp2
102 #define _hw_cfctd_clock_xor123 , HW_E_TBI // ti1s= (p. 393)
103 
104 #define _hwx_cfctd_clock_from_apb1_psc(h,o,k,...) \
105  h##_write(o,sms,0); \
106  HW_B(_hwx_cfctd_kdir,_hw_is_direction_##k)(h,o,k,__VA_ARGS__)
107 #define _hwx_cfctd_clock_ti1fp1(h,o,k,...) \
108  h##_write(o,sms,7); \
109  h##_write(o,ts,5); \
110  HW_B(_hwx_cfctd_kdir,_hw_is_direction_##k)(h,o,k,__VA_ARGS__)
111 #define _hwx_cfctd_clock_ti1fp2(h,o,k,...) \
112  h##_write(o,sms,7); \
113  h##_write(o,ts,6); \
114  HW_B(_hwx_cfctd_kdir,_hw_is_direction_##k)(h,o,k,__VA_ARGS__)
115 
116 
117 /* Mode 'counter' - Mandatory parameter `direction`
118  */
119 #define _hwx_cfctd_kdir0(h,o,k,...) HW_E(HW_EM_AN(k,direction))
120 #define _hwx_cfctd_kdir1(h,o,k,v,...) HW_B(_hwx_cfctd_vdir,_hw_cfctd_dir_##v)(h,o,v,__VA_ARGS__)
121 
122 #define _hw_cfctd_dirs (up_loop,up_noloop,down_loop,down_noloop,updown_loop,updown_noloop)
123 // , jump, v = cms dir opm
124 #define _hw_cfctd_dir_up_loop , _hwx_cfctd_kocf0, 0 // 00 0 0
125 #define _hw_cfctd_dir_up_noloop , _hwx_cfctd_kocf0, 1 // 00 0 1
126 #define _hw_cfctd_dir_down_loop , _hwx_cfctd_kocf0, 2 // 00 1 0
127 #define _hw_cfctd_dir_down_noloop , _hwx_cfctd_kocf0, 3 // 00 1 1
128 #define _hw_cfctd_dir_updown_loop , _hwx_cfctd_vdir2, 12 // 11 x 0
129 #define _hw_cfctd_dir_updown_noloop , _hwx_cfctd_vdir2, 13 // 11 x 1
130 
131 #define _hwx_cfctd_vdir0(h,o,v,...) HW_E(HW_EM_VAL(v,direction,_hw_cfctd_dirs))
132 #define _hwx_cfctd_vdir1(h,o,v,k,...) \
133  uint8_t cmsdiropm = HW_A2(_hw_cfctd_dir_##v) ; \
134  HW_A1(_hw_cfctd_dir_##v)(h,o,k,__VA_ARGS__)
135 
136 #define _hwx_cfctd_vdir2(h,o,k,...) HW_B(_hwx_cfctd_kocf,_hw_is_compare_flag_##k)(h,o,k,__VA_ARGS__)
137 
138 /* Optionnal parameter `compare_flag`, only when counting up-down
139  */
140 #define _hwx_cfctd_kocf1(h,o,k,v,...) HW_B(_hwx_cfctd_vocf,_hw_cfctd_compare_flag_##v)(h,o,v,__VA_ARGS__)
141 #define _hwx_cfctd_vocf0(h,o,v,...) HW_E(HW_EM_VOAL(v,compare_flag,(counting_up,counting_down,counting_up_or_down)))
142 #define _hwx_cfctd_vocf1(h,o,v,k,...) \
143  cmsdiropm += HW_A1(_hw_cfctd_compare_flag_##v); \
144  h##_write(o,cmsdiropm,cmsdiropm); \
145  HW_B(_hwx_cfctd_kpsc,_hw_is_prescaler_##k)(h,o,k,__VA_ARGS__)
146 /* HW_B(_hwx_cfctd_kloop,_hw_is_loop_##k)(h,o,k,__VA_ARGS__) */
147 
148 #define _hwx_cfctd_kocf0(h,o,k,...) \
149  h##_write(o,cmsdiropm,cmsdiropm); \
150  HW_B(_hwx_cfctd_kpsc,_hw_is_prescaler_##k)(h,o,k,__VA_ARGS__)
151 /* HW_B(_hwx_cfctd_kloop,_hw_is_loop_##k)(h,o,k,__VA_ARGS__) */
152 
153 #define _hw_cfctd_compare_flag_counting_down , -8
154 #define _hw_cfctd_compare_flag_counting_up , -4
155 #define _hw_cfctd_compare_flag_counting_up_or_down , +0
156 
157 /* Optionnal parameter `loop`
158  */
159 /* #define _hwx_cfctd_kloop1(h,o,k,v,...) HW_B(_hwx_cfctd_vloop,_hw_state_##v)(h,o,v,__VA_ARGS__) */
160 /* #define _hwx_cfctd_vloop0(h,o,v,...) HW_E(HW_EM_ST(v)) */
161 /* #define _hwx_cfctd_vloop1(h,o,v,k,...) \ */
162 /* h##_write(o,opm,HW_A2(_hw_state_##v)); \ */
163 /* HW_B(_hwx_cfctd_kpsc,_hw_is_prescaler_##k)(h,o,k,__VA_ARGS__) */
164 
165 /* #define _hwx_cfctd_kloop0(h,o,k,...) \ */
166 /* HW_B(_hwx_cfctd_kpsc,_hw_is_prescaler_##k)(h,o,k,__VA_ARGS__) */
167 
168 /* Optionnal parameter `prescaler`
169  */
170 #define _hwx_cfctd_kpsc1(h,o,k0,v,k,...) \
171  h##_write(o,psc,(uint16_t)(v)); \
172  HW_B(_hwx_cfctd_krld,_hw_is_reload_##k)(h,o,k,__VA_ARGS__)
173 #define _hwx_cfctd_kpsc0(h,o,k,...) \
174  HW_B(_hwx_cfctd_krld,_hw_is_reload_##k)(h,o,k,__VA_ARGS__)
175 
176 /* Optionnal parameter `reload`
177  */
178 #define _hwx_cfctd_krld1(h,o,k0,v,k,...) \
179  h##_write(o,arr,(uint16_t)(v)); \
180  HW_B(_hwx_cfctd_krun,_hw_is_run_##k)(h,o,k,__VA_ARGS__)
181 #define _hwx_cfctd_krld0(h,o,k,...) \
182  HW_B(_hwx_cfctd_krun,_hw_is_run_##k)(h,o,k,__VA_ARGS__)
183 
184 /* Optionnal parameter `run`
185  */
186 #define _hwx_cfctd_krun1(h,o,k,v,...) HW_B(_hwx_cfctd_vrun,_hw_state_##v)(h,o,v,__VA_ARGS__)
187 #define _hwx_cfctd_vrun0(h,o,v,...) HW_E(HW_EM_ST(v))
188 #define _hwx_cfctd_vrun1(h,o,v,...) h##_write(o,cen,HW_A1(_hw_state_##v)); HW_EOL(__VA_ARGS__);
189 #define _hwx_cfctd_krun0(h,o,k,...) HW_EOL(__VA_ARGS__)
190 
191 
247 #define hw_run__cta , _hw_rnctd
248 #define _hw_rnctd(o,a,...) _hw_write(o,cen,1) HW_EOL(__VA_ARGS__)
249 
250 #define hwa_run__cta , _hwa_rnctd
251 #define _hwa_rnctd(o,a,...) _hwa_write(o,cen,1) HW_EOL(__VA_ARGS__)
252 
253 
263 #define hw_stop__cta , _hw_spctd
264 #define _hw_spctd(o,a,...) _hw_write(o,cen,0) HW_EOL(__VA_ARGS__)
265 
266 #define hwa_stop__cta , _hwa_spctd
267 #define _hwa_spctd(o,a,...) _hwa_write(o,cen,0) HW_EOL(__VA_ARGS__)
268 
269 
279 #define hw_read__cta , _hw_rdctd
280 #define _hw_rdctd(o,a,...) _hw_read(o,cnt)
281 
282 
292 #define hw_write__cta , _hw_wrctd
293 #define _hw_wrctd(o,a,v,...) _hw_write(o,cnt,(v) & 0xFFFF) HW_EOL(__VA_ARGS__)
294 
295 
305 #define hw_stat__cta , _hw_stctd
306 #define _hw_stctd(o,a,...) _hw_read(o,sr)
307 
308 
309 /*******************************************************************************
310  * *
311  * Context management *
312  * *
313  *******************************************************************************/
314 
315 #define _hwa_setup__cta(o,a) \
316  _hwa_setup_r( o, cr1 ); \
317  _hwa_setup_r( o, cr2 ); \
318  _hwa_setup_r( o, smcr ); \
319  _hwa_setup_r( o, dier ); \
320  _hwa_setup_r( o, ccmr1 ); \
321  _hwa_setup_r( o, ccmr2 ); \
322  _hwa_setup_r( o, ccer ); \
323  _hwa_setup_r( o, psc ); \
324  _hwa_setup_r( o, arr ); \
325  _hwa_setup_r( o, ccr1 ); \
326  _hwa_setup_r( o, ccr2 ); \
327  _hwa_setup_r( o, ccr3 ); \
328  _hwa_setup_r( o, ccr4 )
329 
330 #define _hwa_init__cta(o,a) \
331  _hwa_init_r( o, cr1, 0x00000000 ); \
332  _hwa_init_r( o, cr2, 0x00000000 ); \
333  _hwa_init_r( o, smcr, 0x00000000 ); \
334  _hwa_init_r( o, dier, 0x00000000 ); \
335  _hwa_init_r( o, ccmr1, 0x00000000 ); \
336  _hwa_init_r( o, ccmr2, 0x00000000 ); \
337  _hwa_init_r( o, ccer, 0x00000000 ); \
338  _hwa_init_r( o, psc, 0x00000000 ); \
339  _hwa_init_r( o, arr, 0x00000000 ); \
340  _hwa_init_r( o, ccr1, 0x00000000 ); \
341  _hwa_init_r( o, ccr2, 0x00000000 ); \
342  _hwa_init_r( o, ccr3, 0x00000000 ); \
343  _hwa_init_r( o, ccr4, 0x00000000 )
344 
345 #define _hwa_commit__cta(o,a) \
346  _hwa_commit_r( o, cr1 ); \
347  _hwa_commit_r( o, cr2 ); \
348  _hwa_commit_r( o, smcr ); \
349  _hwa_commit_r( o, dier ); \
350  _hwa_commit_r( o, ccmr1 ); \
351  _hwa_commit_r( o, ccmr2 ); \
352  _hwa_commit_r( o, ccer ); \
353  _hwa_commit_r( o, psc ); \
354  _hwa_commit_r( o, arr ); \
355  _hwa_commit_r( o, ccr1 ); \
356  _hwa_commit_r( o, ccr2 ); \
357  _hwa_commit_r( o, ccr3 ); \
358  _hwa_commit_r( o, ccr4 )
cca_2.h
Counter capture/compare channel.