HWA
Bare metal programming with style
cta_2.h
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/* This file is part of the HWA project.
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* Copyright (c) 2017 Christophe Duparquet.
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* All rights reserved. Read LICENSE.TXT for details.
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*/
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/* Load the channels interface definitions
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*/
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#include "
cca_2.h
"
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#define hw_class__cta
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#define hw_configure__cta , _hw_cfctd
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#define hwa_configure__cta , _hwa_cfctd
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#define _hw_cfctd(o,a,k,...) do{ HW_B(_hwx_cfctd,k)(_hw,o,k,__VA_ARGS__) }while(0)
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#define _hwa_cfctd(o,a,k,...) do{ HW_B(_hwx_cfctd,k)(_hwa,o,k,__VA_ARGS__) }while(0)
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/* At least one keyword
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*/
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#define _hwx_cfctd1(...) HW_E(HW_EM_AML((clock,direction)))
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#define _hwx_cfctd0(h,o,k,...) HW_B(_hwx_cfctd_kmode,_hw_is_mode_##k)(h,o,k,__VA_ARGS__)
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/* Optionnal parameter `mode`
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*/
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#define _hw_cfctd_mode_counter , _hwx_cfctd
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#define _hw_cfctd_mode_encoder , HW_E_TBI
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#define _hw_cfctd_mode_slave , HW_E_TBI
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#define _hwx_cfctd_kmode0(...) _hwx_cfctd(__VA_ARGS__)
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#define _hwx_cfctd_kmode1(h,o,k,v,...) HW_B(_hwx_cfctd_vmode,_hw_cfctd_mode_##v)(h,o,v,__VA_ARGS__)
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#define _hwx_cfctd_vmode1(h,o,v,...) HW_A1(_hw_cfctd_mode_##v)(h,o,__VA_ARGS__)
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#define _hwx_cfctd_vmode0(h,o,v,...) HW_E(HW_EM_VAL(v,mode,(counter,encoder,slave)))
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/* Mode 'counter' - Mandatory parameter `clock`
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*/
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#define _hwx_cfctd(h,o,k,...) HW_B(_hwx_cfctd_kclock,_hw_is_clock_##k)(h,o,k,__VA_ARGS__)
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#define _hwx_cfctd_kclock0(h,o,k,...) HW_E(HW_EM_AN(k,clock))
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#define _hwx_cfctd_kclock1(h,o,k,v,...) HW_B(_hwx_cfctd_vclock,_hw_cfctd_clock_##v)(h,o,v,__VA_ARGS__)
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#define _hwx_cfctd_vclock0(h,o,v,...) HW_E(HW_EM_VAL(v,clock,_hw_cfctd_clocks))
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#define _hwx_cfctd_vclock1(h,o,v,...) HW_A1(_hw_cfctd_clock_##v)(h,o,__VA_ARGS__)
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#define _hw_cfctd_clocks (from_apb1_psc,ti1,ti2,xor123)
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#define _hw_cfctd_clock_from_apb1_psc , _hwx_cfctd_clock_from_apb1_psc
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#define _hw_cfctd_clock_ti1fed , HW_E_TBI
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#define _hw_cfctd_clock_channel1 , _hwx_cfctd_clock_ti1fp1
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#define _hw_cfctd_clock_channel2 , _hwx_cfctd_clock_ti2fp2
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#define _hw_cfctd_clock_xor123 , HW_E_TBI // ti1s= (p. 393)
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#define _hwx_cfctd_clock_from_apb1_psc(h,o,k,...) \
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h##_write(o,sms,0); \
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HW_B(_hwx_cfctd_kdir,_hw_is_direction_##k)(h,o,k,__VA_ARGS__)
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#define _hwx_cfctd_clock_ti1fp1(h,o,k,...) \
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h##_write(o,sms,7); \
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h##_write(o,ts,5); \
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HW_B(_hwx_cfctd_kdir,_hw_is_direction_##k)(h,o,k,__VA_ARGS__)
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#define _hwx_cfctd_clock_ti1fp2(h,o,k,...) \
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h##_write(o,sms,7); \
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h##_write(o,ts,6); \
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HW_B(_hwx_cfctd_kdir,_hw_is_direction_##k)(h,o,k,__VA_ARGS__)
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/* Mode 'counter' - Mandatory parameter `direction`
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*/
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#define _hwx_cfctd_kdir0(h,o,k,...) HW_E(HW_EM_AN(k,direction))
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#define _hwx_cfctd_kdir1(h,o,k,v,...) HW_B(_hwx_cfctd_vdir,_hw_cfctd_dir_##v)(h,o,v,__VA_ARGS__)
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#define _hw_cfctd_dirs (up_loop,up_noloop,down_loop,down_noloop,updown_loop,updown_noloop)
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// , jump, v = cms dir opm
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#define _hw_cfctd_dir_up_loop , _hwx_cfctd_kocf0, 0 // 00 0 0
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#define _hw_cfctd_dir_up_noloop , _hwx_cfctd_kocf0, 1 // 00 0 1
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#define _hw_cfctd_dir_down_loop , _hwx_cfctd_kocf0, 2 // 00 1 0
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#define _hw_cfctd_dir_down_noloop , _hwx_cfctd_kocf0, 3 // 00 1 1
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#define _hw_cfctd_dir_updown_loop , _hwx_cfctd_vdir2, 12 // 11 x 0
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#define _hw_cfctd_dir_updown_noloop , _hwx_cfctd_vdir2, 13 // 11 x 1
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#define _hwx_cfctd_vdir0(h,o,v,...) HW_E(HW_EM_VAL(v,direction,_hw_cfctd_dirs))
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#define _hwx_cfctd_vdir1(h,o,v,k,...) \
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uint8_t cmsdiropm = HW_A2(_hw_cfctd_dir_##v) ; \
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HW_A1(_hw_cfctd_dir_##v)(h,o,k,__VA_ARGS__)
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#define _hwx_cfctd_vdir2(h,o,k,...) HW_B(_hwx_cfctd_kocf,_hw_is_compare_flag_##k)(h,o,k,__VA_ARGS__)
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/* Optionnal parameter `compare_flag`, only when counting up-down
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*/
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#define _hwx_cfctd_kocf1(h,o,k,v,...) HW_B(_hwx_cfctd_vocf,_hw_cfctd_compare_flag_##v)(h,o,v,__VA_ARGS__)
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#define _hwx_cfctd_vocf0(h,o,v,...) HW_E(HW_EM_VOAL(v,compare_flag,(counting_up,counting_down,counting_up_or_down)))
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#define _hwx_cfctd_vocf1(h,o,v,k,...) \
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cmsdiropm += HW_A1(_hw_cfctd_compare_flag_##v); \
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h##_write(o,cmsdiropm,cmsdiropm); \
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HW_B(_hwx_cfctd_kpsc,_hw_is_prescaler_##k)(h,o,k,__VA_ARGS__)
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/* HW_B(_hwx_cfctd_kloop,_hw_is_loop_##k)(h,o,k,__VA_ARGS__) */
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#define _hwx_cfctd_kocf0(h,o,k,...) \
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h##_write(o,cmsdiropm,cmsdiropm); \
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HW_B(_hwx_cfctd_kpsc,_hw_is_prescaler_##k)(h,o,k,__VA_ARGS__)
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/* HW_B(_hwx_cfctd_kloop,_hw_is_loop_##k)(h,o,k,__VA_ARGS__) */
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#define _hw_cfctd_compare_flag_counting_down , -8
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#define _hw_cfctd_compare_flag_counting_up , -4
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#define _hw_cfctd_compare_flag_counting_up_or_down , +0
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/* Optionnal parameter `loop`
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*/
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/* #define _hwx_cfctd_kloop1(h,o,k,v,...) HW_B(_hwx_cfctd_vloop,_hw_state_##v)(h,o,v,__VA_ARGS__) */
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/* #define _hwx_cfctd_vloop0(h,o,v,...) HW_E(HW_EM_ST(v)) */
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/* #define _hwx_cfctd_vloop1(h,o,v,k,...) \ */
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/* h##_write(o,opm,HW_A2(_hw_state_##v)); \ */
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/* HW_B(_hwx_cfctd_kpsc,_hw_is_prescaler_##k)(h,o,k,__VA_ARGS__) */
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/* #define _hwx_cfctd_kloop0(h,o,k,...) \ */
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/* HW_B(_hwx_cfctd_kpsc,_hw_is_prescaler_##k)(h,o,k,__VA_ARGS__) */
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/* Optionnal parameter `prescaler`
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*/
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#define _hwx_cfctd_kpsc1(h,o,k0,v,k,...) \
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h##_write(o,psc,(uint16_t)(v)); \
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HW_B(_hwx_cfctd_krld,_hw_is_reload_##k)(h,o,k,__VA_ARGS__)
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#define _hwx_cfctd_kpsc0(h,o,k,...) \
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HW_B(_hwx_cfctd_krld,_hw_is_reload_##k)(h,o,k,__VA_ARGS__)
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/* Optionnal parameter `reload`
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*/
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#define _hwx_cfctd_krld1(h,o,k0,v,k,...) \
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h##_write(o,arr,(uint16_t)(v)); \
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HW_B(_hwx_cfctd_krun,_hw_is_run_##k)(h,o,k,__VA_ARGS__)
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#define _hwx_cfctd_krld0(h,o,k,...) \
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HW_B(_hwx_cfctd_krun,_hw_is_run_##k)(h,o,k,__VA_ARGS__)
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/* Optionnal parameter `run`
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*/
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#define _hwx_cfctd_krun1(h,o,k,v,...) HW_B(_hwx_cfctd_vrun,_hw_state_##v)(h,o,v,__VA_ARGS__)
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#define _hwx_cfctd_vrun0(h,o,v,...) HW_E(HW_EM_ST(v))
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#define _hwx_cfctd_vrun1(h,o,v,...) h##_write(o,cen,HW_A1(_hw_state_##v)); HW_EOL(__VA_ARGS__);
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#define _hwx_cfctd_krun0(h,o,k,...) HW_EOL(__VA_ARGS__)
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#define hw_run__cta , _hw_rnctd
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#define _hw_rnctd(o,a,...) _hw_write(o,cen,1) HW_EOL(__VA_ARGS__)
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#define hwa_run__cta , _hwa_rnctd
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#define _hwa_rnctd(o,a,...) _hwa_write(o,cen,1) HW_EOL(__VA_ARGS__)
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#define hw_stop__cta , _hw_spctd
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#define _hw_spctd(o,a,...) _hw_write(o,cen,0) HW_EOL(__VA_ARGS__)
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#define hwa_stop__cta , _hwa_spctd
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#define _hwa_spctd(o,a,...) _hwa_write(o,cen,0) HW_EOL(__VA_ARGS__)
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#define hw_read__cta , _hw_rdctd
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#define _hw_rdctd(o,a,...) _hw_read(o,cnt)
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#define hw_write__cta , _hw_wrctd
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#define _hw_wrctd(o,a,v,...) _hw_write(o,cnt,(v) & 0xFFFF) HW_EOL(__VA_ARGS__)
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#define hw_stat__cta , _hw_stctd
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#define _hw_stctd(o,a,...) _hw_read(o,sr)
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/*******************************************************************************
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* *
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* Context management *
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* *
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*******************************************************************************/
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#define _hwa_setup__cta(o,a) \
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_hwa_setup_r( o, cr1 ); \
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_hwa_setup_r( o, cr2 ); \
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_hwa_setup_r( o, smcr ); \
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_hwa_setup_r( o, dier ); \
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_hwa_setup_r( o, ccmr1 ); \
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_hwa_setup_r( o, ccmr2 ); \
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_hwa_setup_r( o, ccer ); \
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_hwa_setup_r( o, psc ); \
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_hwa_setup_r( o, arr ); \
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_hwa_setup_r( o, ccr1 ); \
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_hwa_setup_r( o, ccr2 ); \
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_hwa_setup_r( o, ccr3 ); \
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_hwa_setup_r( o, ccr4 )
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#define _hwa_init__cta(o,a) \
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_hwa_init_r( o, cr1, 0x00000000 ); \
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_hwa_init_r( o, cr2, 0x00000000 ); \
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_hwa_init_r( o, smcr, 0x00000000 ); \
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_hwa_init_r( o, dier, 0x00000000 ); \
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_hwa_init_r( o, ccmr1, 0x00000000 ); \
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_hwa_init_r( o, ccmr2, 0x00000000 ); \
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_hwa_init_r( o, ccer, 0x00000000 ); \
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_hwa_init_r( o, psc, 0x00000000 ); \
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_hwa_init_r( o, arr, 0x00000000 ); \
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_hwa_init_r( o, ccr1, 0x00000000 ); \
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_hwa_init_r( o, ccr2, 0x00000000 ); \
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_hwa_init_r( o, ccr3, 0x00000000 ); \
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_hwa_init_r( o, ccr4, 0x00000000 )
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#define _hwa_commit__cta(o,a) \
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_hwa_commit_r( o, cr1 ); \
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_hwa_commit_r( o, cr2 ); \
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_hwa_commit_r( o, smcr ); \
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_hwa_commit_r( o, dier ); \
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_hwa_commit_r( o, ccmr1 ); \
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_hwa_commit_r( o, ccmr2 ); \
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_hwa_commit_r( o, ccer ); \
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_hwa_commit_r( o, psc ); \
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_hwa_commit_r( o, arr ); \
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_hwa_commit_r( o, ccr1 ); \
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_hwa_commit_r( o, ccr2 ); \
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_hwa_commit_r( o, ccr3 ); \
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_hwa_commit_r( o, ccr4 )
cca_2.h
Counter capture/compare channel.
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