HWA
Bare metal programming with style
swtwimaster.h
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/* This file is part of the HWA project.
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* Copyright (c) 2018 Christophe Duparquet.
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* All rights reserved. Read LICENSE.TXT for details.
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*/
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#if !defined DOXYGEN && !defined HW_DEVICE_ARCH_AVR
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# warning Class _swtwimaster may not be supported by your hardware
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#endif
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#define hw_class__swtwimaster
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#define HW_SWTWIMASTER(...) _HW_SWTWIM_(__VA_ARGS__,,,,,,,)
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#define _HW_SWTWIM_(k,...) HW_BW(_HW_SWTWIM_1,scl,k)(k,__VA_ARGS__)
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#define _HW_SWTWIM_10(k,...) _HW_SWTWIM_E(k,__VA_ARGS__)
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#define _HW_SWTWIM_11(k,...) _HW_SWTWIM_12(HW_AD(__VA_ARGS__))
/* Get SCL def */
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#define _HW_SWTWIM_12(...) _HW_SWTWIM_13(__VA_ARGS__)
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#define _HW_SWTWIM_13(scl,...) HW_B(_HW_SWTWIM_13,HW_A0 scl)(scl,__VA_ARGS__)
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#define _HW_SWTWIM_131(scl,...) ,HW_SWTWIMASTER,HW_SWTWIMASTER(...): HW_A2 scl
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#define _HW_SWTWIM_130(scl,k,...) HW_BW(_HW_SWTWIM_2,sda,k)(scl,k,__VA_ARGS__)
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#define _HW_SWTWIM_20(scl,k,...) _HW_SWTWIM_E(k,__VA_ARGS__)
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#define _HW_SWTWIM_21(scl,k,...) _HW_SWTWIM_22(scl,HW_AD(__VA_ARGS__))
/* Get SDA def */
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#define _HW_SWTWIM_22(...) _HW_SWTWIM_23(__VA_ARGS__)
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#define _HW_SWTWIM_23(scl,sda,...) HW_B(_HW_SWTWIM_23,HW_A0 sda)(scl,sda,__VA_ARGS__)
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#define _HW_SWTWIM_231(scl,sda,...) ,HW_SWTWIMASTER,HW_SWTWIMASTER(...): HW_A2 sda
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#define _HW_SWTWIM_230(scl,sda,k,...) HW_BW(_HW_SWTWIM_3,bps,k)(HW_A1 scl,scl,sda,k,__VA_ARGS__)
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#define _HW_SWTWIM_30(sclo,scl,sda,k,...) _HW_SWTWIM_E(k,__VA_ARGS__)
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#define _HW_SWTWIM_31(sclo,scl,sda,k,bps,g,...) HW_B(_HW_SWTWIM_4,g)(sclo,scl,sda,bps,g,__VA_ARGS__)
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#define _HW_SWTWIM_40(sclo,scl,sda,bps,...) _HW_SWTWIM_E(k,__VA_ARGS__)
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#define _HW_SWTWIM_41(sclo,scl,sda,bps,...) _swtwimaster,swtwimaster_##sclo,(-1,scl,sda,bps)
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//#define _HW_SWTWIM_E(k,...) HW_E(HW_EM_SY("HW_SWTWIM(scl,..., sda,..., bps,...)" (k,__VA_ARGS__)))
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#define _HW_SWTWIM_E(...) ,HW_SWTWIMASTER(),HW_EM_SY("HW_SWTWIMASTER(scl,..., sda,..., bps,...)")
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#define HW_DECLARE__swtwimaster , _hw_dcswtwimaster
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#define _hw_dcswtwimaster(o,a,...) HW_BV(_hw_dcswtwimaster,declare_,HW_A0(__VA_ARGS__),o)
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#define _hw_dcswtwimaster0(v,...) HW_E(HW_EM_OVL(v,(weak)))
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#define _hw_dcswtwimaster1(weak,o) \
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\
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extern uint8_t _hw_##o##__sr ; \
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\
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void weak _hw_##o##__delay ( ); \
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void weak _hw_##o##_start ( ); \
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void weak _hw_##o##_slar ( uint8_t ); \
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void weak _hw_##o##_slaw ( uint8_t ); \
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uint8_t weak _hw_##o##_write ( uint8_t ); \
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uint8_t weak _hw_##o##_write ( uint8_t ); \
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void weak _hw_##o##_stop ( ); \
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uint8_t weak _hw_##o##_start_read_stop ( uint8_t ); \
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void weak _hw_##o##_start_write_stop ( uint8_t, uint8_t )
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#define HW_IMPLEMENT__swtwimaster , _hw_dfswtwimaster
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#define _hw_dfswtwimaster(o,a,scl,sda,bps,...) \
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\
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extern void _hw_##o##__delay ( ) ; \
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\
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uint8_t _hw_##o##__sr ; \
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\
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void _hw_##o##__delay ( ) { \
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hw_waste_cycles( HW_SYSHZ / (2*bps) - 8
/* CALL+RET */
); \
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} \
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\
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void _hw_##o##_start ( ) { \
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/* SDA goes low while SCL is high */
\
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_hw( configure, sda, mode, digital_output ); \
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_hw_##o##__delay(); \
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_hw( configure, scl, mode, digital_output ); \
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} \
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\
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void _hw_##o##_slar ( uint8_t sla ) { \
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uint8_t ack = _hw_##o##_write( (sla<<1) + 1 ); \
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if ( ack == 0 ) \
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_hw_##o##__sr = 0x40 ;
/* HW_TWI_MR_SLA_ACK */
\
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else \
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_hw_##o##__sr = 0x48 ;
/* HW_TWI_MR_SLA_NACK */
\
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} \
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\
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void _hw_##o##_slaw ( uint8_t sla ) { \
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uint8_t ack = _hw_##o##_write( (sla<<1) + 0 ); \
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if ( ack == 0 ) \
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_hw_##o##__sr = 0x18 ;
/* HW_TWI_MT_SLA_ACK */
\
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else \
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_hw_##o##__sr = 0x20 ;
/* HW_TWI_MT_SLA_NACK */
\
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} \
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\
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uint8_t _hw_##o##_write ( uint8_t byte ) { \
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/* SDA can change while SCL is low */
\
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for ( uint8_t bit=0x80 ; bit ; bit>>=1 ) { \
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if ( (byte & bit) == 0 ) \
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_hw( configure, sda, mode, digital_output ); \
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else { \
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_hw( configure, sda, mode, digital_input ); \
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while ( !hw(read, sda) ) {} \
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} \
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_hw( configure, scl, mode, digital_input ); \
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while ( !hw(read, scl) ) {}
/* The slave can extend the SCL low period */
\
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_hw_##o##__delay(); \
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_hw( configure, scl, mode, digital_output ) ; \
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} \
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_hw( configure, sda, mode, digital_input ); \
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_hw( configure, scl, mode, digital_input ); \
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while ( !hw(read, scl) ) {}
/* The slave can extend the SCL low period */
\
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_hw_##o##__delay(); \
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byte = hw(read, sda); \
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_hw( configure, scl, mode, digital_output ) ; \
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return byte ; \
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} \
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\
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uint8_t _hw_##o##__read ( ) { \
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/* SDA can change while SCL is low */
\
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uint8_t data = 0 ; \
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for ( uint8_t bit=0x80 ; bit ; bit>>=1 ) { \
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_hw( configure, scl, mode, digital_input ); \
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while ( !hw(read, scl) ) {}
/* The slave can extend the SCL low period */
\
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_hw_##o##__delay(); \
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if ( hw(read, sda) != 0 ) \
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data |= bit ; \
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_hw( configure, scl, mode, digital_output ) ; \
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_hw_##o##__delay(); \
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} \
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return data ; \
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} \
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\
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uint8_t _hw_##o##_read_ack ( ) { \
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uint8_t data = _hw_##o##__read(); \
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_hw( configure, sda, mode, digital_output ) ; \
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_hw( configure, scl, mode, digital_input ); \
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_hw_##o##__delay(); \
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while ( !hw(read, scl) ) {}
/* The slave can extend the SCL low period */
\
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_hw( configure, scl, mode, digital_output ) ; \
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_hw_##o##__delay(); \
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return data ; \
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} \
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\
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uint8_t _hw_##o##_read_nack ( ) { \
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uint8_t data = _hw_##o##__read(); \
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_hw( configure, scl, mode, digital_input ); \
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_hw_##o##__delay(); \
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while ( !hw(read, scl) ) {}
/* The slave can extend the SCL low period */
\
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_hw( configure, scl, mode, digital_output ) ; \
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_hw( configure, sda, mode, digital_output ) ; \
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_hw_##o##__delay(); \
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return data ; \
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} \
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\
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void _hw_##o##_stop ( ) { \
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/* SDA goes high while SCL is high */
\
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if ( hw(read, sda) ) \
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_hw( configure, sda, mode, digital_output ) ; \
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_hw( configure, scl, mode, digital_input ); \
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_hw_##o##__delay(); \
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_hw( configure, sda, mode, digital_input ); \
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} \
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\
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void _hw_##o##_start_write_stop ( uint8_t sla, uint8_t v ) \
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{ \
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_hw_##o##_start(); \
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_hw_##o##_slaw(sla); \
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_hw_##o##_write(v); \
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_hw_##o##_stop(); \
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} \
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\
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uint8_t _hw_##o##_start_read_stop ( uint8_t sla ) \
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{ \
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_hw_##o##_start(); \
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_hw_##o##_slar(sla); \
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uint8_t v = _hw_##o##_read_nack(); \
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_hw_##o##_stop(); \
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return v; \
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} \
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\
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extern uint8_t hw_foo()
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#define hw_configure__swtwimaster , _hw_cfswtwimaster
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/* SCL and SDA are set to 0 and then configured as digital_input /
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* digital_output. External pullup resistors are required.
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*/
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#define _hw_cfswtwimaster(o,a,scl,sda,bps,...) \
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do{ \
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_hwa_begin_(,); \
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_hwa( configure, scl, mode, digital_input_floating ); \
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_hwa( configure, sda, mode, digital_input_floating ); \
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_hwa( write, scl, 0 ); \
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_hwa( write, sda, 0 ); \
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_hwa_commit_(,); \
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}while(0)
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#define hwa_configure__swtwimaster , _hwa_cfswtwimaster
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#define _hwa_cfswtwimaster(o,a,scl,sda,bps,...) \
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do{ \
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_hwa( configure, scl, mode, digital_input_floating ); \
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_hwa( configure, sda, mode, digital_input_floating ); \
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_hwa( write, scl, 0 ); \
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_hwa( write, sda, 0 ); \
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}while(0)
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#define hw_xfr_start__swtwimaster , _hw_swtwimaster_start
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#define _hw_swtwimaster_start(o,a,scl,sda,bps,...) _hw_##o##_start() HW_EOL(__VA_ARGS__)
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#define hw_xfr_slar__swtwimaster , _hw_swtwimaster_slar
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#define _hw_swtwimaster_slar(o,a,scl,sda,bps,sla,...) _hw_##o##_slar(sla) HW_EOL(__VA_ARGS__)
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#define hw_xfr_slaw__swtwimaster , _hw_swtwimaster_slaw
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#define _hw_swtwimaster_slaw(o,a,scl,sda,bps,sla,...) _hw_##o##_slaw(sla) HW_EOL(__VA_ARGS__)
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#define hw_xfr_read__swtwimaster , _hw_swtwimasterrd
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#define _hw_swtwimasterrd(o,a,k,...) HW_BW(_hw_swtwimasterrdack,ack,k)(o,k,__VA_ARGS__,,)
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#define _hw_swtwimasterrdack1(o,k,...) _hw_##o##_read_ack() HW_EOL(__VA_ARGS__)
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#define _hw_swtwimasterrdack0(o,k,...) HW_BW(_hw_swtwimasterrdnack,nack,k)(o,k,__VA_ARGS__)
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#define _hw_swtwimasterrdnack1(o,ok,k,...) _hw_##o##_read_nack() HW_EOL(__VA_ARGS__)
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#define _hw_swtwimasterrdnack0(o,k,...) HW_E(HW_EM_XNIL(k,(ack,nack)))
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#define hw_xfr_write__swtwimaster , _hw_swtwimaster_write
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#define _hw_swtwimaster_write(o,a,scl,sda,bps,data,...) _hw_##o##_write(data) HW_EOL(__VA_ARGS__)
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#define hw_xfr_stop__swtwimaster , _hw_swtwimaster_stop
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#define _hw_swtwimaster_stop(o,a,scl,sda,bps,...) _hw_##o##_stop() HW_EOL(__VA_ARGS__)
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#define hw_stat__swtwimaster , _hw_swtwimaster_stat
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#define _hw_swtwimaster_stat(o,a,scl,sda,bps,...) _hw_##o##__sr HW_EOL(__VA_ARGS__)
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