HWA
Bare metal programming with style
usarta_1.h
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1 
2 /* This file is part of the HWA project.
3  * Copyright (c) 2019 Christophe Duparquet.
4  * All rights reserved. Read LICENSE.TXT for details.
5  */
6 
26 #define hw_class__usarta
27 
28 /* Hardware registers // Reset value
29  */
30 #define hw__usarta_sr _r32, 0x00, 0x00000360, 0 // 0x00C0
31 #define hw__usarta_dr _r32, 0x04, 0x0000001F, 0 // X
32 #define hw__usarta_brr _r32, 0x08, 0x0000FFFF, 0 // 0
33 #define hw__usarta_cr1 _r32, 0x0C, 0x000003FF, 0 // 0
34 #define hw__usarta_cr2 _r32, 0x10, 0x00007F6F, 0 // 0
35 #define hw__usarta_cr3 _r32, 0x14, 0x000007FF, 0 // 0
36 #define hw__usarta_gtpr _r32, 0x18, 0x0000FFFF, 0 // 0
37 
38 /* Logical registers
39  */
40 #define hw__usarta_reg_cts _cb1, sr, 1, 9
41 #define hw__usarta_lbd _cb1, sr, 1, 8
42 #define hw__usarta_txe _cb1, sr, 1, 7
43 #define hw__usarta_tc _cb1, sr, 1, 6
44 #define hw__usarta_rxne _cb1, sr, 1, 5
45 #define hw__usarta_idle _cb1, sr, 1, 4
46 #define hw__usarta_ore _cb1, sr, 1, 3
47 #define hw__usarta_ne _cb1, sr, 1, 2
48 #define hw__usarta_fe _cb1, sr, 1, 1
49 #define hw__usarta_pe _cb1, sr, 1, 0
50 
51 #define hw__usarta_divmantissa _cb1, brr, 12, 4
52 #define hw__usarta_divfraction _cb1, brr, 4, 0
53 
54 #define hw__usarta_ue _cb1, cr1, 1, 13
55 #define hw__usarta_m _cb1, cr1, 1, 12
56 #define hw__usarta_wake _cb1, cr1, 1, 11
57 #define hw__usarta_pce _cb1, cr1, 1, 10
58 #define hw__usarta_ps _cb1, cr1, 1, 9
59 #define hw__usarta_peie _cb1, cr1, 1, 8
60 #define hw__usarta_txeie _cb1, cr1, 1, 7
61 #define hw__usarta_tcie _cb1, cr1, 1, 6
62 #define hw__usarta_rxneie _cb1, cr1, 1, 5
63 #define hw__usarta_idleie _cb1, cr1, 1, 4
64 #define hw__usarta_te _cb1, cr1, 1, 3
65 #define hw__usarta_re _cb1, cr1, 1, 2
66 #define hw__usarta_rwu _cb1, cr1, 1, 1
67 #define hw__usarta_sbk _cb1, cr1, 1, 0
68 
69 #define hw__usarta_linen _cb1, cr2, 1, 14
70 #define hw__usarta_stop _cb1, cr2, 2, 12
71 #define hw__usarta_clken _cb1, cr2, 1, 11
72 #define hw__usarta_cpol _cb1, cr2, 1, 10
73 #define hw__usarta_cpha _cb1, cr2, 1, 9
74 #define hw__usarta_lbcl _cb1, cr2, 1, 8
75 #define hw__usarta_lbdie _cb1, cr2, 1, 6
76 #define hw__usarta_lbdl _cb1, cr2, 1, 5
77 #define hw__usarta_add _cb1, cr2, 4, 0
78 
79 #define hw__usarta_ctsie _cb1, cr3, 1, 10
80 #define hw__usarta_ctse _cb1, cr3, 1, 9
81 #define hw__usarta_rtse _cb1, cr3, 1, 8
82 #define hw__usarta_dmat _cb1, cr3, 1, 7
83 #define hw__usarta_dmar _cb1, cr3, 1, 6
84 #define hw__usarta_scen _cb1, cr3, 1, 5
85 #define hw__usarta_nack _cb1, cr3, 1, 4
86 #define hw__usarta_hdsel _cb1, cr3, 1, 3
87 #define hw__usarta_irlp _cb1, cr3, 1, 2
88 #define hw__usarta_iren _cb1, cr3, 1, 1
89 #define hw__usarta_eie _cb1, cr3, 1, 0
90 
91 #define hw__usarta_gt _cb1, gtpr, 8, 8
92 #define hw__usarta_psc _cb1, gtpr, 8, 0
93 
94 
95 #if !defined __ASSEMBLER__
96 
97 typedef struct {
98  hwa_r32_t brr ;
99  hwa_r32_t cr1 ;
100  hwa_r32_t cr2 ;
101  hwa_r32_t cr3 ;
102  hwa_r32_t gtpr ;
103 } hwa_usarta_t ;
104 
105 #endif