HWA
Bare metal programming with style
attinyx4.h
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1 
2 /* This file is part of the HWA project.
3  * Copyright (c) 2012,2015,2020 Christophe Duparquet.
4  * All rights reserved. Read LICENSE.TXT for details.
5  */
6 
68 #define HW_DEVICE_ATTINYX4
69 
73 #define HW_DEVICE_RAM_START 0x0060
74 
78 #define HW_DEVICE_APP_START 0x0022
79 
84 #include "../hwa_1.h"
85 #include "attinyx4_fuses.h"
86 
87 
88 #define hw_int0_irq _irq, 1, int0, ie, if
89 #define hw_pcic0_irq _irq, 2, pcic0, ie, if
90 #define hw_pcic1_irq _irq, 3, pcic1, ie, if
91 #define hw_watchdog0_irq _irq, 4, watchdog0, ie, if
92 #define hw_counter1_irq_capture0 _irq, 5, counter1, icie0, icif0
93 #define hw_counter1_capture0_irq _irq, 5, counter1, icie0, icif0
94 #define hw_counter1_irq_compare0 _irq, 6, counter1, ocie0, ocif0
95 #define hw_counter1_compare0_irq _irq, 6, counter1, ocie0, ocif0
96 #define hw_counter1_irq_compare1 _irq, 7, counter1, ocie1, ocif1
97 #define hw_counter1_compare1_irq _irq, 7, counter1, ocie1, ocif1
98 #define hw_counter1_irq_overflow _irq, 8, counter1, ie, if
99 #define hw_counter1_irq _irq, 8, counter1, ie, if
100 #define hw_counter0_irq_compare0 _irq, 9, counter0, ocie0, ocif0
101 #define hw_counter0_compare0_irq _irq, 9, counter0, ocie0, ocif0
102 #define hw_counter0_irq_compare1 _irq, 10, counter0, ocie1, ocif1
103 #define hw_counter0_compare1_irq _irq, 10, counter0, ocie1, ocif1
104 #define hw_counter0_irq_overflow _irq, 11, counter0, ie, if
105 #define hw_counter0_irq _irq, 11, counter0, ie, if
106 #define hw_acmp0_irq _irq, 12, acmp0, ie, if
107 #define hw_adc0_irq _irq, 13, adc0, ie, if
108 #define hw_eeprom0_irq _irq, 14, eeprom0, sie, /* no irq flag */
109 #define hw_eeprom0_irq_ready _irq, 14, eeprom0, sie,
110 #define hw_usi0_irq_start _irq, 15, usi0, ies, ifs
111 #define hw_usi0_irq_overflow _irq, 16, usi0, ieov, ifov
112 #define hw_usi0_irq_txc _irq, 16, usi0, ieov, ifov
113 #define hw_usi0_irq _irq, 16, usi0, ieov, ifov
114 
115 
116 /*******************************************************************************
117  * *
118  * Shared registers *
119  * *
120  * This is an object used to gather hardware registers shared *
121  * by other objects *
122  * *
123  *******************************************************************************/
124 
125 #define hw_class__shared
126 #define hw_shared _shared, 0
127 
128 #define hw_shared_gimsk _r8, 0x5B, 0x70, 0x00
129 #define hw_shared_gifr _r8, 0x5A, 0x70, 0x70
130 #define hw_shared_timsk _r8, 0x59, 0x7E, 0x00
131 #define hw_shared_tifr _r8, 0x58, 0x7E, 0x7E
132 #define hw_shared_gtccr _r8, 0x43, 0x81, 0x00
133 #define hw_shared_prr _r8, 0x40, 0x0F, 0x00
134 #define hw_shared_gpior2 _r8, 0x35, 0xFF, 0x00
135 #define hw_shared_gpior1 _r8, 0x34, 0xFF, 0x00
136 #define hw_shared_gpior0 _r8, 0x33, 0xFF, 0x00
137 #define hw_shared_did _r8, 0x21, 0xFF, 0x00
138 
139 /* FIXME: find a way for HW_X() to expand that correctly (without inserting the
140  * name in second position)
141  */
142 #define hw_gpior2 _xb1, gpior2, shared, 8, 0
143 #define hw_gpior1 _xb1, gpior1, shared, 8, 0
144 #define hw_gpior0 _m11,(shared,gpior0),shared,gpior0,_r8,0 +0x33,0xFF,0x00,8,0;
145 
146 
147 #if !defined __ASSEMBLER__
148 /*
149  * HWA context
150  */
151 typedef struct {
152 
153  /* Hardware registers
154  */
155  hwa_r8_t gimsk ;
156  hwa_r8_t gifr ;
157  hwa_r8_t timsk ;
158  hwa_r8_t tifr ;
159  hwa_r8_t gtccr ;
160  hwa_r8_t prr ;
161  hwa_r8_t did ;
162 } hwa_shared_t ;
163 #endif
164 
165 
166 /*******************************************************************************
167  * *
168  * Ports and pins *
169  * *
170  *******************************************************************************/
171 
172 
173 #include "../classes/gpa_1.h"
174 #include "../classes/ioa_1.h"
175 
176 
177 /* Objects class, address
178  */
179 
180 #define hw_porta _gpa, 0x39
181 #define hw_portb _gpa, 0x36
182 
183 /* Not-connected pins
184  */
185 #if !defined HW_NC_PB0
186 # define HW_NC_PB0 0
187 #endif
188 
189 #if !defined HW_NC_PB1
190 # define HW_NC_PB1 0
191 #endif
192 
193 #if !defined HW_NC_PB2
194 # define HW_NC_PB2 0
195 #endif
196 
197 #if !defined HW_NC_PB3
198 # define HW_NC_PB3 0
199 #endif
200 
201 #define HW_PORTB_NCMSK HW_NC_PB3*0x08 + HW_NC_PB2*0x04 + HW_NC_PB1*0x02 + HW_NC_PB0
202 
203 #if HW_PORTB_NCMSK
204 # define _hw_portb_ncmsk , HW_PORTB_NCMSK
205 #endif
206 
207 /* Digital input disable bits for analog input pins
208  */
209 #define hw_porta_1_0_did _xb1, shared, did, 1, 0
210 #define hw_porta_1_1_did _xb1, shared, did, 1, 1
211 #define hw_porta_1_2_did _xb1, shared, did, 1, 2
212 #define hw_porta_1_3_did _xb1, shared, did, 1, 3
213 #define hw_porta_1_4_did _xb1, shared, did, 1, 4
214 #define hw_porta_1_5_did _xb1, shared, did, 1, 5
215 #define hw_porta_1_6_did _xb1, shared, did, 1, 6
216 #define hw_porta_1_7_did _xb1, shared, did, 1, 7
217 
218 /* Pin-change controllers
219  */
220 #define hw_porta_pcic pcic0
221 #define hw_portb_pcic pcic1
222 
223 /* Canonical pin names
224  */
225 #define hw_pin_ain0 _ioa, porta, 1, 1
226 #define hw_pin_ain1 _ioa, porta, 1, 2
227 
228 #define hw_pin_usck _ioa, porta, 1, 4
229 #define hw_pin_do _ioa, porta, 1, 5
230 #define hw_pin_di _ioa, porta, 1, 6
231 
232 //#define hw_pin_icp _ioa, porta, 1, 7
233 
234 #define hw_pin_adc0 _ioa, porta, 1, 0
235 #define hw_pin_adc1 _ioa, porta, 1, 1
236 #define hw_pin_adc2 _ioa, porta, 1, 2
237 #define hw_pin_adc3 _ioa, porta, 1, 3
238 #define hw_pin_adc4 _ioa, porta, 1, 4
239 #define hw_pin_adc5 _ioa, porta, 1, 5
240 #define hw_pin_adc6 _ioa, porta, 1, 6
241 #define hw_pin_adc7 _ioa, porta, 1, 7
242 
243 #define hw_pin_int0 _ioa, portb, 1, 2
244 
245 #if defined HW_DEVICE_PACKAGE_14P3
246 #
247 # define hw_pin_2 _ioa, portb, 1, 0
248 # define hw_pin_3 _ioa, portb, 1, 1
249 # define hw_pin_4 _ioa, portb, 1, 3
250 # define hw_pin_5 _ioa, portb, 1, 2
251 # define hw_pin_6 _ioa, porta, 1, 7
252 # define hw_pin_7 _ioa, porta, 1, 6
253 # define hw_pin_8 _ioa, porta, 1, 5
254 # define hw_pin_9 _ioa, porta, 1, 4
255 # define hw_pin_10 _ioa, porta, 1, 3
256 # define hw_pin_11 _ioa, porta, 1, 2
257 # define hw_pin_12 _ioa, porta, 1, 1
258 # define hw_pin_13 _ioa, porta, 1, 0
259 #
260 #endif
261 
262 
263 /*******************************************************************************
264  * *
265  * Core *
266  * *
267  *******************************************************************************/
268 
269 #include "../classes/corea_1.h"
270 
271 /* Object class, address
272  */
273 #define hw_core0 _corea, 0
274 
275 /* Class hardware registers class, address, write mask, flags mask
276  */
277 #define hw__corea_sreg _r8, 0x5F, 0xFF, 0x00
278 #define hw__corea_sph _r8, 0x5E, 0x03, 0x00
279 #define hw__corea_spl _r8, 0x5D, 0xFF, 0x00
280 
281 /* Object hardware registers class, address, write mask, flags mask
282  */
283 #define hw_core0_mcucr _r8, 0x55, 0xFF, 0x00
284 #define hw_core0_mcusr _r8, 0x54, 0x0F, 0x00
285 #define hw_core0_osccal _r8, 0x51, 0xFF, 0x00
286 
287 /* Object logical registers
288  */
289 #define hw_core0_bods _ob1, mcucr, 1, 7
290 #define hw_core0_pud _ob1, mcucr, 1, 6
291 #define hw_core0_se _ob1, mcucr, 1, 5
292 #define hw_core0_sm _ob1, mcucr, 2, 3
293 #define hw_core0_bodse _ob1, mcucr, 1, 2
294 
295 #define hw_core0_wdrf _ob1, mcusr, 1, 3
296 #define hw_core0_borf _ob1, mcusr, 1, 2
297 #define hw_core0_extrf _ob1, mcusr, 1, 1
298 #define hw_core0_porf _ob1, mcusr, 1, 0
299 #define hw_core0_allrf _ob1, mcusr, 4, 0 /* convenient */
300 
301 
302 /*******************************************************************************
303  * *
304  * External interrupt controller *
305  * *
306  *******************************************************************************/
307 
308 /* Object class, address
309  */
310 #include "../classes/inta_1.h"
311 #define hw_int0 _inta, 0
312 
313 #define hw_int0_sc _xb1, core0, mcucr, 2, 0
314 #define hw_int0_ie _xb1, shared, gimsk, 1, 6
315 #define hw_int0_if _xb1, shared, gifr, 1, 6
316 
317 
318 /*******************************************************************************
319  * *
320  * Pin-change interrupt controllers *
321  * *
322  *******************************************************************************/
323 
324 #include "../classes/pxa_1.h"
325 
326 /* Object class, address
327  */
328 #define hw_pcic0 _pxa, 0x32
329 
330 /* Object hardware registers class, address, write mask, flags mask
331  */
332 #define hw_pcic0_msk _r8, 0x00, 0xFF, 0x00
333 
334 /* Object logical registers
335  */
336 #define hw_pcic0_ie _xb1, shared, gimsk, 1, 4
337 #define hw_pcic0_if _xb1, shared, gifr, 1, 4
338 
339 /* Object class, address
340  */
341 #define hw_pcic1 _pxa, 0x40
342 
343 /* Object hardware registers class, address, write mask, flags mask
344  */
345 #define hw_pcic1_msk _r8, 0x00, 0x0F, 0x00
346 
347 /* Object logical registers
348  */
349 #define hw_pcic1_ie _xb1, shared, gimsk, 1, 5
350 #define hw_pcic1_if _xb1, shared, gifr, 1, 5
351 
352 
353 /*******************************************************************************
354  * *
355  * Watchdog *
356  * *
357  *******************************************************************************/
358 
359 /* Object class, address
360  */
361 #include "../classes/wda_1.h"
362 #define hw_watchdog0 _wda, 0
363 
364 /* Class registers class, address, write mask, flags mask
365  */
366 #define hw__wda_csr _r8, 0x41, 0xFF, 0x80
367 
368 #define hw__wda_if _cb1, csr, 1, 7
369 #define hw__wda_ie _cb1, csr, 1, 6
370 #define hw__wda_wdp _cb2, csr, 1, 5, 3, csr, 3, 0, 0
371 #define hw__wda_wdce _cb1, csr, 1, 4
372 #define hw__wda_wde _cb1, csr, 1, 3
373 
374 #define hw__wda_eie _cb2, csr, 1, 3, 1, csr, 1, 6, 0 /* convenient */
375 #define hw__wda_ifie _cb1, csr, 2, 6 /* convenient for clearing irq */
376 
377 #define hw__wda_wdrf _xb1, core0, mcusr, 1, 3
378 
379 
380 /*******************************************************************************
381  * *
382  * Counter 0/1 prescaler *
383  * *
384  *******************************************************************************/
385 
386 #include "../classes/psa_1.h"
387 
388 /* Object class, address
389  */
390 #define hw_prescaler0 _psa, 0
391 
392 /* Object logical registers
393  */
394 #define hw_prescaler0_tsm _xb1, shared, gtccr, 1, 7
395 #define hw_prescaler0_psr _xb1, shared, gtccr, 1, 0
396 
397 /* This is a convenient logical register definition for stopping the prescaler
398  */
399 #define hw_prescaler0_tsmpsr _xb2, shared, gtccr, 1, 7, 1, gtccr, 1, 0, 0
400 
401 
402 /*******************************************************************************
403  * *
404  * Counter 0 *
405  * *
406  *******************************************************************************/
407 
408 /* Object class, address
409  */
410 #include "../classes/oca_1.h"
411 #include "../classes/cta_1.h"
412 
413 #define hw_counter0 _cta, 0
414 
415 /* Hardware registers class, address, write mask, flags mask
416  */
417 #define hw_counter0_ocr1 _r8, 0x5C, 0xFF, 0x00 /* OCR0B */
418 #define hw_counter0_imsk _r8, 0x59, 0x07, 0x00
419 #define hw_counter0_ifr _r8, 0x58, 0x07, 0x07
420 #define hw_counter0_ocr0 _r8, 0x56, 0xFF, 0x00 /* OCR0A */
421 #define hw_counter0_ccrb _r8, 0x53, 0xCF, 0x00
422 #define hw_counter0_count _r8, 0x52, 0xFF, 0x00
423 #define hw_counter0_ccra _r8, 0x50, 0xF3, 0x00
424 
425 /* Logical registers
426  */
427 #define hw_counter0_com0 _ob1, ccra, 2, 6
428 #define hw_counter0_com1 _ob1, ccra, 2, 4
429 #define hw_counter0_wgm _ob2, ccra, 2, 0, 0, ccrb, 1, 3, 2
430 #define hw_counter0_foc1 _ob1, ccrb, 1, 6
431 #define hw_counter0_foc0 _ob1, ccrb, 1, 7
432 #define hw_counter0_cs _ob1, ccrb, 3, 0
433 #define hw_counter0_ocie1 _ob1, imsk, 1, 2
434 #define hw_counter0_ocie0 _ob1, imsk, 1, 1
435 #define hw_counter0_ie _ob1, imsk, 1, 0
436 #define hw_counter0_ocif1 _ob1, ifr, 1, 2
437 #define hw_counter0_ocif0 _ob1, ifr, 1, 1
438 #define hw_counter0_if _ob1, ifr, 1, 0
439 
440 /* Relatives
441  */
442 #define hw_counter0_prescaler0 prescaler0
443 #define hw_counter0_prescaler prescaler0
444 
445 #define hw_counter0_compare0 _oca, counter0, 0
446 #define hw_counter0_compare0_pin _ioa, portb, 1, 2
447 #define hw_counter0_compare0_counter counter0
448 
449 #define hw_counter0_compare1 _oca, counter0, 1
450 #define hw_counter0_compare1_pin _ioa, porta, 1, 7
451 #define hw_counter0_compare1_counter counter0
452 
453 
454 /*******************************************************************************
455  * *
456  * Counter 1 *
457  * *
458  *******************************************************************************/
459 
460 #include "../classes/occ_1.h"
461 #include "../classes/ica_1.h"
462 #include "../classes/ctd_1.h"
463 
464 /* Object class, address
465  */
466 #define hw_counter1 _ctd, 0
467 
468 /* Hardware registers class, address, write mask, flags mask
469  */
470 #define hw_counter1_ccra _r8, 0x4F, 0xF3, 0x00
471 #define hw_counter1_ccrb _r8, 0x4E, 0xDF, 0x00
472 #define hw_counter1_ocr0 _r16, 0x4A, 0xFFFF, 0x0000 /* OCR1A */
473 #define hw_counter1_ocr1 _r16, 0x48, 0xFFFF, 0x0000 /* OCR1B */
474 #define hw_counter1_icr0 _r16, 0x44, 0xFFFF, 0x0000 /* ICR1 */
475 #define hw_counter1_ccrc _r8, 0x42, 0xC0, 0x00
476 #define hw_counter1_count _r16, 0x4C, 0xFFFF, 0x0000
477 #define hw_counter1_imsk _r8, 0x2C, 0x27, 0x00
478 #define hw_counter1_ifr _r8, 0x2B, 0x27, 0x27
479 
480 /* Logical registers
481  */
482 #define hw_counter1_com0 _ob1, ccra, 2, 6
483 #define hw_counter1_com1 _ob1, ccra, 2, 4
484 #define hw_counter1_icnc _ob1, ccrb, 1, 7
485 #define hw_counter1_ices _ob1, ccrb, 1, 6
486 #define hw_counter1_cs _ob1, ccrb, 3, 0
487 #define hw_counter1_wgm _ob2, ccrb, 2, 3, 2, ccra, 2, 0, 0
488 #define hw_counter1_foc0 _ob1, ccrc, 1, 7
489 #define hw_counter1_foc1 _ob1, ccrc, 1, 6
490 #define hw_counter1_icie0 _ob1, imsk, 1, 5
491 #define hw_counter1_ocie1 _ob1, imsk, 1, 2
492 #define hw_counter1_ocie0 _ob1, imsk, 1, 1
493 #define hw_counter1_ie _ob1, imsk, 1, 0
494 #define hw_counter1_icif0 _ob1, ifr, 1, 5
495 #define hw_counter1_ocif1 _ob1, ifr, 1, 2
496 #define hw_counter1_ocif0 _ob1, ifr, 1, 1
497 #define hw_counter1_if _ob1, ifr, 1, 0
498 
499 #define hw_counter1_acic _xb1, acmp0, csr, 1, 2
500 
501 /* Relatives
502  */
503 #define hw_counter1_prescaler0 prescaler0
504 #define hw_counter1_prescaler prescaler0
505 
506 #define hw_counter1_compare0 _occ, counter1, 0
507 #define hw_counter1_compare0_pin _ioa, porta, 1, 6
508 #define hw_counter1_compare0_counter counter1
509 
510 #define hw_counter1_compare1 _occ, counter1, 1
511 #define hw_counter1_compare1_pin _ioa, porta, 1, 5
512 #define hw_counter1_compare1_counter counter1
513 
514 #define hw_counter1_capture0 _ica, counter1, 0
515 #define hw_counter1_capture0_pin _ioa, porta, 1, 7
516 #define hw_counter1_capture0_counter counter1
517 
518 
519 /*******************************************************************************
520  * *
521  * Universal Serial Interface *
522  * *
523  *******************************************************************************/
524 
525 /* Instance class, address
526  */
527 #include "../classes/usia_1.h"
528 #define hw_usi0 _usia, 0x2D
529 
530 /* Class registers class, address, write mask, flags mask
531  */
532 #define hw__usia_cr _r8, 0, 0xFF, 0x00
533 #define hw__usia_sr _r8, 1, 0xFF, 0xE0
534 #define hw__usia_dr _r8, 2, 0xFF, 0x00
535 #define hw__usia_br _r8, 3, 0xFF, 0x00
536 
537 #define hw__usia_ies _cb1, cr, 1, 7
538 #define hw__usia_ieov _cb1, cr, 1, 6
539 #define hw__usia_wm _cb1, cr, 2, 4
540 #define hw__usia_cs _cb1, cr, 2, 2
541 #define hw__usia_clk _cb1, cr, 1, 1
542 #define hw__usia_tc _cb1, cr, 1, 0
543 
544 #define hw__usia_ifs _cb1, sr, 1, 7
545 #define hw__usia_ifov _cb1, sr, 1, 6
546 #define hw__usia_pf _cb1, sr, 1, 5
547 #define hw__usia_dc _cb1, sr, 1, 4
548 #define hw__usia_cnt _cb1, sr, 4, 0
549 
550 
551 /* USI used as SPI master with software clock
552  */
553 #define hw_spimaster_swclk0 _usia_spimaster_swclk, usi0
554 
555 /* USI used as SPI master with counter0 overflow clock
556  */
557 #define hw_spimaster_c0clk0 _usia_spimaster_c0clk, usi0
558 
559 /* Pins
560  */
561 #define hw_usi0_ck _ioa, porta, 1, 4
562 #define hw_usi0_do _ioa, porta, 1, 5
563 #define hw_usi0_di _ioa, porta, 1, 6
564 
565 
566 /*******************************************************************************
567  * *
568  * Analog Comparator *
569  * *
570  *******************************************************************************/
571 
572 /* Instance class, address
573  */
574 #include "../classes/aca_1.h"
575 #define hw_acmp0 _aca, 0
576 
577 /* Class registers class, address, write mask, flags mask
578  */
579 #define hw__aca_csr _r8, 0x28, 0xDF, 0x10
580 
581 /* Object registers class, address, write mask, flags mask
582  *
583 * Required for _hw_counter1_acic
584  */
585 #define hw_acmp0_csr _r8, 0x28, 0xDF, 0x10
586 
587 #define hw_acmp0_acme _xb1, adc0, srb, 1, 6
588 #define hw_acmp0_aden _xb1, adc0, sra, 1, 7
589 #define hw_acmp0_admux _xb1, adc0, admux, 6, 0
590 
591 
592 /*******************************************************************************
593  * *
594  * Analog-to-Digital Converter *
595  * *
596  *******************************************************************************/
597 
598 #include "../classes/ada_1.h"
599 #define hw_adc0 _ada, 0
600 
601 #define hw__ada_admux _r8, 0x27, 0xFF, 0x00
602 #define hw__ada_sra _r8, 0x26, 0xFF, 0x10
603 #define hw__ada_adc _r16, 0x24, 0x0000, 0x0000
604 #define hw__ada_adch _r8, 0x25, 0x00, 0x00
605 #define hw__ada_adcl _r8, 0x24, 0x00, 0x00
606 #define hw__ada_srb _r8, 0x23, 0xD7, 0x00
607 
608 #define hw_adc0_admux _r8, 0x27, 0xFF, 0x00
609 #define hw_adc0_sra _r8, 0x26, 0xFF, 0x10
610 #define hw_adc0_srb _r8, 0x23, 0xD7, 0x00
611 
612 #define hw__ada_refs _cb1, admux, 2, 6
613 #define hw__ada_mux _cb1, admux, 6, 0
614 
615 #define hw__ada_en _cb1, sra, 1, 7
616 #define hw__ada_sc _cb1, sra, 1, 6
617 #define hw__ada_ate _cb1, sra, 1, 5
618 #define hw__ada_if _cb1, sra, 1, 4
619 #define hw__ada_ie _cb1, sra, 1, 3
620 #define hw__ada_ps _cb1, sra, 3, 0
621 
622 #define hw__ada_bin _cb1, srb, 1, 7
623 #define hw__ada_lar _cb1, srb, 1, 4
624 #define hw__ada_ts _cb1, srb, 3, 0
625 
626 
627 /*******************************************************************************
628  * *
629  * EEPROM memory *
630  * *
631  *******************************************************************************/
632 
633 /* Class
634  */
635 #define hw_class__eea
636 
637 /* Object class, address
638  */
639 #define hw_eeprom0 _eea, 0
640 
641 /* Class regs class, address, write mask, flags mask
642  */
643 #define hw__eea_arh _r8, 0x3F, 0x01, 0x00
644 #define hw__eea_arl _r8, 0x3E, 0xFF, 0x00
645 #define hw__eea_ar _r16, 0x3E, 0x01FF, 0x00
646 #define hw__eea_dr _r8, 0x3D, 0xFF, 0x00
647 #define hw__eea_cr _r8, 0x3C, 0x3F, 0x00
648 
649 #define hw__eea_pm _cb1, cr, 2, 4
650 #define hw__eea_rie _cb1, cr, 1, 3
651 #define hw__eea_mpe _cb1, cr, 1, 2
652 #define hw__eea_pe _cb1, cr, 1, 1
653 #define hw__eea_re _cb1, cr, 1, 0
654 
655 
656 /*******************************************************************************
657  * *
658  * Flash memory *
659  * *
660  *******************************************************************************/
661 
662 /* Class
663  */
664 #define hw_class__fla
665 
666 /* Object class, address
667  */
668 #define hw_flash0 _fla, 0
669 
670 /* Class regs class, address, write mask, flags mask
671  */
672 #define hw__fla_csr _r8, 0x57, 0x3F, 0x00
673 
674 #define hw__fla_sigrd _cb1, csr, 1, 5
675 #define hw__fla_rsig _cb1, csr, 1, 5 /* old definition */
676 #define hw__fla_rwwsre _cb1, csr, 1, 4
677 #define hw__fla_ctpb _cb1, csr, 1, 4 /* old definition */
678 #define hw__fla_blbset _cb1, csr, 1, 3
679 #define hw__fla_rflb _cb1, csr, 1, 3 /* old definition */
680 #define hw__fla_pgwrt _cb1, csr, 1, 2
681 #define hw__fla_pgers _cb1, csr, 1, 1
682 #define hw__fla_spmen _cb1, csr, 1, 0
683 
684 
685 #if !defined __ASSEMBLER__
686 
687 /* This structure is instanciated by hwa( begin ) or hwa( begin, reset ) and
688  * used by all HWA asynchronous instructions to bufferize hardware accesses.
689  */
690 typedef struct {
691  uint8_t commit ;
693  hwa_shared_t shared ;
694 
695  hwa_corea_t core0 ;
696  hwa_gpa_t porta ;
697  hwa_gpa_t portb ;
698  hwa_pxa_t pcic0 ;
699  hwa_pxa_t pcic1 ;
700  hwa_wda_t watchdog0 ;
701  hwa_cta_t counter0 ;
702  hwa_ctd_t counter1 ;
703  hwa_usia_t usi0 ;
704  hwa_aca_t acmp0 ;
705  hwa_ada_t adc0 ;
706 } hwa_t ;
707 
708 #include "../hwa_2.h"
709 #include "../classes/c1_2.h"
710 #include "../classes/corea_2.h"
711 #include "../classes/inta_2.h"
712 #include "../classes/ioa_2.h"
713 #include "../classes/gpa_2.h"
714 #include "../classes/pxa_2.h"
715 #include "../classes/wda_2.h"
716 #include "../classes/psa_2.h"
717 #include "../classes/oca_2.h"
718 #include "../classes/cta_2.h"
719 #include "../classes/occ_2.h"
720 #include "../classes/ica_2.h"
721 #include "../classes/ctd_2.h"
722 #include "../classes/usia_2.h"
723 #include "../classes/aca_2.h"
724 #include "../classes/ada_2.h"
725 #include "../classes/eea_2.h"
726 #include "../classes/fla_2.h"
727 
728 
729 HW_INLINE void _hwa_setup_context( hwa_t *hwa )
730 {
731  _hwa_setup_r( shared, gimsk );
732  _hwa_setup_r( shared, gifr );
733  _hwa_setup_r( shared, prr );
734  _hwa_setup_r( shared, gtccr );
735  _hwa_setup_r( shared, timsk );
736  _hwa_setup_r( shared, tifr );
737  _hwa_setup_r( shared, did );
738 
739  _hwa_setup_o( core0 );
740  _hwa_setup_o( porta );
741  _hwa_setup_o( portb );
742  _hwa_setup_o( pcic0 );
743  _hwa_setup_o( pcic1 );
744  _hwa_setup_o( watchdog0 );
745  _hwa_setup_o( counter0 );
746  _hwa_setup_o( counter1 );
747  _hwa_setup_o( usi0 );
748  _hwa_setup_o( adc0 );
749  _hwa_setup_o( acmp0 );
750 }
751 
752 
753 HW_INLINE void _hwa_init_context( hwa_t *hwa )
754 {
755  _hwa_init_r( shared, gimsk, 0 );
756  _hwa_init_r( shared, gifr, 0 );
757  _hwa_init_r( shared, prr, 0 );
758  _hwa_init_r( shared, gtccr, 0 );
759  _hwa_init_r( shared, timsk, 0 );
760  _hwa_init_r( shared, tifr, 0 );
761  _hwa_init_r( shared, did, 0 );
762 
763  _hwa_init_o( core0 );
764  _hwa_init_o( porta );
765  _hwa_init_o( portb );
766  _hwa_init_o( pcic0 );
767  _hwa_init_o( pcic1 );
768  _hwa_init_o( watchdog0 );
769  _hwa_init_o( counter0 );
770  _hwa_init_o( counter1 );
771  _hwa_init_o( usi0 );
772  _hwa_init_o( adc0 );
773  _hwa_init_o( acmp0 );
774 }
775 
776 
777 HW_INLINE void _hwa_commit_context( hwa_t *hwa )
778 {
779  /* Solve the configuration of the counters
780  *
781  * The configuration values are written here since the solve function only
782  * has the address of the counter and does not know its name.
783  */
784  _hwa_solve_o( counter0 );
785  _hwa_solve_o( counter1 );
786 
787  _hwa_commit_r( shared, gimsk );
788  _hwa_commit_r( shared, gifr );
789  _hwa_commit_o( core0 );
790  _hwa_commit_r( shared, prr );
791 
792  _hwa_commit_o( watchdog0 );
793  _hwa_commit_o( porta );
794  _hwa_commit_o( portb );
795 
796  _hwa_commit_o( pcic0 );
797  _hwa_commit_o( pcic1 );
798 
799  _hwa_commit_r( shared, gtccr );
800  _hwa_commit_o( counter0 );
801  _hwa_commit_o( counter1 );
802 
803  _hwa_commit_o( usi0 );
804  _hwa_commit_o( adc0 );
805  _hwa_commit_r( shared, did );
806  _hwa_commit_o( acmp0 );
807 }
808 
809 #endif /* !defined __ASSEMBLER__ */
_hwa_init_r
#define _hwa_init_r(o, r, v)
Initialize an HWA register of an object with its reset value.
Definition: hwa_2.h:369
_hwa_init_o
#define _hwa_init_o(o)
Initialize the HWA context registers of an object with their reset value.
Definition: hwa_2.h:331
_hwa_solve_o
#define _hwa_solve_o(o)
Solve the configuration of an object.
Definition: hwa_2.h:340
hwa
#define hwa(...)
hwa( action, object [,...] ) stores an action for an object into a HWA context.
Definition: hwa_macros.h:552
_hwa_setup_r
#define _hwa_setup_r(o, r)
Create a HWA register.
Definition: hwa_2.h:359
_hwa_commit_r
#define _hwa_commit_r(o, r)
Commit one object hardware register.
Definition: hwa_2.h:379
_hwa_commit_o
#define _hwa_commit_o(o)
Commit the registers of an object.
Definition: hwa_2.h:349
_hwa_setup_o
#define _hwa_setup_o(o)
Initialize the HWA context registers addresses of an object.
Definition: hwa_2.h:322