HWA
Bare metal programming with style
attinyx5.h
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1 
2 /* This file is part of the HWA project.
3  * Copyright (c) 2012,2015 Christophe Duparquet.
4  * All rights reserved. Read LICENSE.TXT for details.
5  */
6 
57 #define HW_DEVICE_ATTINYX5
58 
62 #define HW_DEVICE_RAM_START 0x0060
63 
67 #define HW_DEVICE_APP_START 0x001E
68 
72 #include "../hwa_1.h"
73 #include "attinyx5_fuses.h"
74 
75 
76 #define hw_int0_irq _irq, 1, int0, ie, if
77 #define hw_pcic0_irq _irq, 2, pcic0, ie, if
78 #define hw_counter1_compare0_irq _irq, 3, counter1, ocie0, ocif0
79 #define hw_counter1_irq _irq, 4, counter1, ie, if
80 #define hw_counter1_irq_overflow _irq, 4, counter1, ie, if
81 #define hw_counter0_irq _irq, 5, counter0, ie, if
82 #define hw_counter0_irq_overflow _irq, 5, counter0, ie, if
83 #define hw_eeprom0_irq _irq, 6, eeprom0, ie, /* no irq flag */
84 #define hw_eeprom0_irq_ready _irq, 6, eeprom0, ie,
85 #define hw_acmp0_irq _irq, 7, acmp0, ie, if
86 #define hw_adc0_irq _irq, 8, adc0, ie, if
87 #define hw_counter1_compare1_irq _irq, 9, counter1, ocie1, ocif1
88 #define hw_counter0_compare0_irq _irq, 10, counter0, ocie0, ocif0
89 #define hw_counter0_compare1_irq _irq, 11, counter0, ocie1, ocif1
90 #define hw_watchdog0_irq _irq, 12, watchdog0, ie, if
91 #define hw_usi0_irq _irq, , , ,
92 #define hw_usi0_irq_start _irq, 13, usi0, ies, ifs
93 #define hw_usi0_irq_overflow _irq, 14, usi0, ieov, ifov
94 #define hw_usi0_irq_txc _irq, 14, usi0, ieov, ifov
95 
96 
97 /*******************************************************************************
98  * *
99  * Peripherals *
100  * *
101  *******************************************************************************/
102 
103 /*******************************************************************************
104  * *
105  * Shared registers *
106  * *
107  * This is an object used to gather hardware registers shared *
108  * by other objects *
109  * *
110  *******************************************************************************/
111 
112 #define hw_class__shared
113 
114 /* Object class, address
115  */
116 #define hw_shared _shared, 0
117 
118 /* Object hardware registers class, address, write mask, flags mask
119  */
120 #define hw_shared_gimsk _r8, 0x5B, 0x60, 0x00
121 #define hw_shared_gifr _r8, 0x5A, 0x60, 0x60
122 #define hw_shared_timsk _r8, 0x59, 0x7E, 0x00
123 #define hw_shared_tifr _r8, 0x58, 0x7E, 0x7E
124 #define hw_shared_gtccr _r8, 0x4C, 0xFF, 0x00
125 #define hw_shared_prr _r8, 0x40, 0x0F, 0x00
126 #define hw_shared_gpior2 _r8, 0x33, 0xFF, 0x00
127 #define hw_shared_gpior1 _r8, 0x32, 0xFF, 0x00
128 #define hw_shared_gpior0 _r8, 0x31, 0xFF, 0x00
129 #define hw_shared_did _r8, 0x34, 0x3F, 0x00
130 
131 
132 #if !defined __ASSEMBLER__
133 
134 /* HWA context
135  */
136 typedef struct {
137 
138  /* Hardware registers
139  */
140  hwa_r8_t gimsk ;
141  hwa_r8_t gifr ;
142  hwa_r8_t timsk ;
143  hwa_r8_t tifr ;
144  hwa_r8_t gtccr ;
145  hwa_r8_t prr ;
146  hwa_r8_t did ;
147 } hwa_shared_t ;
148 
149 #endif
150 
151 
152 /*******************************************************************************
153  * *
154  * Ports and pins *
155  * *
156  *******************************************************************************/
157 
158 #include "../classes/gpa_1.h"
159 #include "../classes/ioa_1.h"
160 
161 /* Object class, address
162  */
163 #define hw_portb _gpa, 0x36
164 
165 /* Not-connected pins
166  */
167 #if !defined HW_NC_PB3
168 # define HW_NC_PB3 0
169 #endif
170 
171 #if !defined HW_NC_PB4
172 # define HW_NC_PB4 0
173 #endif
174 
175 #if !defined HW_NC_PB5
176 # define HW_NC_PB5 0
177 #endif
178 
179 #define HW_PORTB_NCMSK (0xC0 + HW_NC_PB5*0x20 + HW_NC_PB4*0x10 + HW_NC_PB3*0x08)
180 
181 #define _hw_portb_ncmsk , HW_PORTB_NCMSK
182 
183 /* Digital input disable bits for analog input pins
184  */
185 #define hw_portb_1_5_did _xb1, shared, did, 1, 5 /* ADC0 PB5 */
186 #define hw_portb_1_4_did _xb1, shared, did, 1, 4 /* ADC2 PB4 */
187 #define hw_portb_1_3_did _xb1, shared, did, 1, 3 /* ADC3 PB3 */
188 #define hw_portb_1_2_did _xb1, shared, did, 1, 2 /* ADC1 PB2 */
189 #define hw_portb_1_1_did _xb1, shared, did, 1, 1 /* AIN1 PB1 */
190 #define hw_portb_1_0_did _xb1, shared, did, 1, 0 /* AIN0 PB0 */
191 
192 /* Relatives
193  */
194 #define hw_portb_pcic pcic0
195 //#define hw_portb_pcic _pxa, 0, ~HW_PORTB_NCMSK
196 
197 
198 /* (pin,...) notation
199  */
200 #define hw_pin_usck _ioa, portb, 1, 2
201 #define hw_pin_int0 _ioa, portb, 1, 2
202 #define hw_pin_do _ioa, portb, 1, 1
203 #define hw_pin_di _ioa, portb, 1, 0
204 
205 #if defined HW_DEVICE_PACKAGE_8P3
206 # define hw_pin_1 _ioa, portb, 1, 5
207 # define hw_pin_2 _ioa, portb, 1, 3
208 # define hw_pin_3 _ioa, portb, 1, 4
209 # define hw_pin_5 _ioa, portb, 1, 0
210 # define hw_pin_6 _ioa, portb, 1, 1
211 # define hw_pin_7 _ioa, portb, 1, 2
212 #endif
213 
214 
215 /*******************************************************************************
216  * *
217  * Core *
218  * *
219  *******************************************************************************/
220 
221 /* Object class, address
222  */
223 #include "../classes/corea_1.h"
224 #define hw_core0 _corea, 0
225 
226 /* Class hardware registers class, address, write mask, flags mask
227  */
228 #define hw__corea_sreg _r8, 0x5F, 0xFF, 0x00
229 #define hw__corea_sph _r8, 0x5E, 0x03, 0x00
230 #define hw__corea_spl _r8, 0x5D, 0xFF, 0x00
231 
232 /* Object hardware registers class, address, write mask, flags mask
233  */
234 #define hw_core0_mcucr _r8, 0x55, 0xFF, 0x00
235 #define hw_core0_mcusr _r8, 0x54, 0x0F, 0x00
236 #define hw_core0_osccal _r8, 0x51, 0xFF, 0x00
237 
238 /* Object logical registers
239  */
240 #define hw_core0_bods _ob1, mcucr, 1, 7
241 #define hw_core0_pud _ob1, mcucr, 1, 6
242 #define hw_core0_se _ob1, mcucr, 1, 5
243 #define hw_core0_sm _ob1, mcucr, 2, 3
244 #define hw_core0_bodse _ob1, mcucr, 1, 2
245 #define hw_core0_isc0 _ob1, mcucr, 2, 0
246 
247 #define hw_core0_wdrf _ob1, mcusr, 1, 3
248 #define hw_core0_borf _ob1, mcusr, 1, 2
249 #define hw_core0_extrf _ob1, mcusr, 1, 1
250 #define hw_core0_porf _ob1, mcusr, 1, 0
251 #define hw_core0_allrf _ob1, mcusr, 4, 0 /* convenient */
252 
253 
254 /*******************************************************************************
255  * *
256  * External interrupt controller *
257  * *
258  *******************************************************************************/
259 
260 /* Object class, address
261  */
262 #include "../classes/inta_1.h"
263 #define hw_int0 _inta, 0
264 
265 #define hw_int0_sc _xb1, core0, mcucr, 2, 0
266 #define hw_int0_ie _xb1, shared, gimsk, 1, 6
267 #define hw_int0_if _xb1, shared, gifr, 1, 6
268 
269 
270 /*******************************************************************************
271  * *
272  * Pin-change interrupt controller *
273  * *
274  *******************************************************************************/
275 
276 /* Object class, address
277  */
278 #include "../classes/pxa_1.h"
279 #define hw_pcic0 _pxa, 0
280 
281 /* Object hardware registers class, address, write mask, flags mask
282  */
283 #define hw_pcic0_msk _r8, 0x35, 0x3F, 0x00
284 
285 /* Object logical registers
286  */
287 #define hw_pcic0_ie _xb1, shared, gimsk, 1, 5
288 #define hw_pcic0_if _xb1, shared, gifr, 1, 5
289 
290 
291 /*******************************************************************************
292  * *
293  * Watchdog *
294  * *
295  *******************************************************************************/
296 
297 /* Object class, address
298  */
299 #include "../classes/wda_1.h"
300 #define hw_watchdog0 _wda, 0
301 
302 /* Class hardware registers class, address, write mask, flags mask
303  */
304 #define hw__wda_csr _r8, 0x41, 0xFF, 0x80
305 
306 /* Class logical registers
307  */
308 #define hw__wda_if _cb1, csr, 1, 7
309 #define hw__wda_ie _cb1, csr, 1, 6
310 #define hw__wda_wdp _cb2, csr, 1, 5, 3, csr, 3, 0, 0
311 #define hw__wda_wdce _cb1, csr, 1, 4
312 #define hw__wda_wde _cb1, csr, 1, 3
313 
314 #define hw__wda_eie _cb2, csr, 1, 3, 1, csr, 1, 6, 0 /* convenient */
315 #define hw__wda_ifie _cb1, csr, 2, 6 /* convenient for clearing irq */
316 
317 #define hw__wda_wdrf _xb1, core0, mcusr, 1, 3
318 
319 
320 /*******************************************************************************
321  * *
322  * Counter 0 *
323  * *
324  *******************************************************************************/
325 
326 #include "../classes/oca_1.h"
327 #include "../classes/cta_1.h"
328 
329 /* Object class, address
330  */
331 #define hw_counter0 _cta, 0
332 
333 /* Object hardware registers class, address, write mask, flags mask
334  */
335 #define hw_counter0_ccra _r8, 0x4A, 0xF3, 0x00
336 #define hw_counter0_ocr0 _r8, 0x49, 0xFF, 0x00 /* OCR0A */
337 #define hw_counter0_ocr1 _r8, 0x48, 0xFF, 0x00 /* OCR0B */
338 #define hw_counter0_ccrb _r8, 0x53, 0xCF, 0x00
339 #define hw_counter0_count _r8, 0x52, 0xFF, 0x00
340 #define hw_counter0_imsk _r8, -1, 0, 0 /* For compatibility */
341 #define hw_counter0_ifr _r8, -1, 0, 0
342 
343 /* Object logical registers
344  */
345 #define hw_counter0_com0 _ob1, ccra, 2, 6
346 #define hw_counter0_com1 _ob1, ccra, 2, 4
347 #define hw_counter0_wgm _ob2, ccra, 2, 0, 0, ccrb, 1, 3, 2
348 #define hw_counter0_foc0 _ob1, ccrb, 1, 7
349 #define hw_counter0_foc1 _ob1, ccrb, 1, 6
350 #define hw_counter0_cs _ob1, ccrb, 3, 0
351 
352 #define hw_counter0_ie _xb1, shared, timsk, 1, 1
353 #define hw_counter0_if _xb1, shared, tifr, 1, 1
354 
355 #define hw_counter0_ocie0 _xb1, shared, timsk, 1, 4
356 #define hw_counter0_ocif0 _xb1, shared, tifr, 1, 4
357 
358 #define hw_counter0_ocie1 _xb1, shared, imsk, 1, 3
359 #define hw_counter0_ocif1 _xb1, shared, ifr, 1, 3
360 
361 /* Relatives
362  */
363 #define hw_counter0_prescaler0 prescaler0
364 #define hw_counter0_prescaler prescaler0
365 
366 #define hw_counter0_compare0 _oca, counter0, 0
367 #define hw_counter0_compare0_pin _ioa, portb, 1, 0
368 #define hw_counter0_compare0_counter counter0
369 
370 #define hw_counter0_compare1 _oca, counter0, 1
371 #define hw_counter0_compare1_pin _ioa, portb, 1, 1
372 #define hw_counter0_compare1_counter counter0
373 
374 
375 /*******************************************************************************
376  * *
377  * Counter 0 prescaler *
378  * *
379  *******************************************************************************/
380 
381 #include "../classes/psa_1.h"
382 
383 /* Object class, address
384  */
385 #define hw_prescaler0 _psa, 0
386 
387 /* Object logical registers
388  */
389 #define hw_prescaler0_tsm _xb1, shared, gtccr, 1, 7
390 #define hw_prescaler0_psr _xb1, shared, gtccr, 1, 0
391 
392 /* This is a convenient logical register definition for stopping the prescaler
393  */
394 #define hw_prescaler0_tsmpsr _xb2, shared, gtccr, 1, 7, 1, gtccr, 1, 0, 0
395 
396 
397 /*******************************************************************************
398  * *
399  * Counter 1 *
400  * *
401  *******************************************************************************/
402 
403 #include "../classes/ocb_1.h"
404 #include "../classes/dtga_1.h"
405 #include "../classes/ctb_1.h"
406 
407 /* Object class, address
408  */
409 #define hw_counter1 _ctb, 0
410 
411 /* Hardware registers class, address, write mask, flags mask
412  */
413 #define hw_counter1_ccr _r8, 0x50, 0xFF, 0x00 /* TCCR1 */
414 #define hw_counter1_count _r8, 0x4F, 0xFF, 0x00 /* TCNT1 */
415 #define hw_counter1_ocr0 _r8, 0x4E, 0xFF, 0x00 /* OCR1A */
416 #define hw_counter1_ocr2 _r8, 0x4D, 0xFF, 0x00 /* OCR1C */
417 #define hw_counter1_ocr1 _r8, 0x4B, 0xFF, 0x00 /* OCR1B */
418 #define hw_counter1_dta _r8, 0x45, 0xFF, 0x00 /* DT1A */
419 #define hw_counter1_dtb _r8, 0x44, 0xFF, 0x00 /* DT1B */
420 #define hw_counter1_dtps _r8, 0x43, 0x03, 0x00 /* DTPS1 */
421 
422 /* Logical registers
423  */
424 #define hw_counter1_ctc _ob1, ccr, 1, 7
425 #define hw_counter1_pwm0 _ob1, ccr, 1, 6
426 #define hw_counter1_com0 _ob1, ccr, 2, 4
427 #define hw_counter1_cs _ob1, ccr, 4, 0
428 
429 #define hw_counter1_dtgps _ob1, dtps, 2, 0
430 #define hw_counter1_dtg0h _ob1, dta, 4, 4
431 #define hw_counter1_dtg0l _ob1, dta, 4, 0
432 #define hw_counter1_dtg1h _ob1, dtb, 4, 4
433 #define hw_counter1_dtg1l _ob1, dtb, 4, 0
434 
435 #define hw_counter1_ocie0 _xb1, shared, timsk, 1, 6
436 #define hw_counter1_ocie1 _xb1, shared, timsk, 1, 5
437 #define hw_counter1_ie _xb1, shared, timsk, 1, 2
438 
439 #define hw_counter1_ocif0 _xb1, shared, tifr, 1, 6
440 #define hw_counter1_ocif1 _xb1, shared, tifr, 1, 5
441 #define hw_counter1_if _xb1, shared, tifr, 1, 2
442 
443 #define hw_counter1_pwm1 _xb1, shared, gtccr, 1, 6
444 #define hw_counter1_com1 _xb1, shared, gtccr, 2, 4
445 #define hw_counter1_foc1 _xb1, shared, gtccr, 1, 3
446 #define hw_counter1_foc0 _xb1, shared, gtccr, 1, 2
447 
448 /* Relatives
449  */
450 #define hw_counter1_prescaler prescaler1
451 #define hw_counter1_prescaler0 prescaler1
452 
453 #define hw_counter1_compare0 _ocb, counter1, 0
454 #define hw_counter1_compare0_pin _ioa, portb, 1, 1
455 #define hw_counter1_compare0_pin_h _ioa, portb, 1, 1
456 #define hw_counter1_compare0_pin_l _ioa, portb, 1, 0
457 #define hw_counter1_compare0_counter counter1
458 #define hw_counter1_compare0_dtg _dtga, counter1, 0
459 
460 #define hw_counter1_compare1 _ocb, counter1, 1
461 #define hw_counter1_compare1_pin _ioa, portb, 1, 4
462 #define hw_counter1_compare1_pin_h _ioa, portb, 1, 4
463 #define hw_counter1_compare1_pin_l _ioa, portb, 1, 3
464 #define hw_counter1_compare1_counter counter1
465 #define hw_counter1_compare1_dtg _dtga, counter1, 1
466 
467 #define hw_counter1_compare2 _xb1, counter1, ocr2, 8, 0
468 
469 
470 /*******************************************************************************
471  * *
472  * Counter 1 prescaler *
473  * *
474  *******************************************************************************/
475 
476 #include "../classes/psb_1.h"
477 
478 /* Object class, address
479  */
480 #define hw_prescaler1 _psb, 0
481 
482 /* Object hardware registers class, address, write mask, flags mask
483  */
484 #define hw_prescaler1_pllcsr _r8, 0x47, 0x86, 0x00 /* PLLCSR */
485 
486 /* Object logical registers
487  */
488 #define hw_prescaler1_psr _xb1, shared, gtccr, 1, 1
489 
490 #define hw_prescaler1_lsm _ob1, pllcsr, 1, 7
491 #define hw_prescaler1_pcke _ob1, pllcsr, 1, 2
492 #define hw_prescaler1_plle _ob1, pllcsr, 1, 1
493 #define hw_prescaler1_plock _ob1, pllcsr, 1, 0
494 
495 
496 /*******************************************************************************
497  * *
498  * Universal Serial Interface *
499  * *
500  *******************************************************************************/
501 
502 #include "../classes/usia_1.h"
503 
504 /* Object class, address
505  */
506 #define hw_usi0 _usia, 0
507 
508 /* Hardware registers class, address, write mask, flags mask
509  */
510 #define hw_usi0_dr _r8, 0x2F, 0xFF, 0x00
511 #define hw_usi0_br _r8, 0x30, 0xFF, 0x00
512 #define hw_usi0_sr _r8, 0x2E, 0xFF, 0xE0
513 #define hw_usi0_cr _r8, 0x2D, 0xFF, 0x00
514 
515 /* Logical registers
516  */
517 #define hw_usi0_ies _ob1, cr, 1, 7
518 #define hw_usi0_ieov _ob1, cr, 1, 6
519 #define hw_usi0_iep _ob1, cr, 1, 5
520 #define hw_usi0_wm _ob1, cr, 2, 4
521 #define hw_usi0_cs _ob1, cr, 2, 2
522 #define hw_usi0_clk _ob1, cr, 1, 1
523 #define hw_usi0_tc _ob1, cr, 1, 0
524 
525 #define hw_usi0_ifs _ob1, sr, 1, 7
526 #define hw_usi0_ifov _ob1, sr, 1, 6
527 #define hw_usi0_ifp _ob1, sr, 1, 5
528 #define hw_usi0_dc _ob1, sr, 1, 4
529 #define hw_usi0_cnt _ob1, sr, 4, 0
530 
531 /* Relatives
532  */
533 #define hw_usi0_ck _ioa, portb, 1, 2
534 #define hw_usi0_do _ioa, portb, 1, 1
535 #define hw_usi0_di _ioa, portb, 1, 0
536 
537 /* USI used as SPI master with software clock
538  * FIXME: should create an object for that.
539  */
540 #define hw_spimaster_swclk0 _usia_spimaster_swclk, usi0
541 
542 /* USI used as SPI master with counter0 overflow clock
543  * FIXME: should create an object for that.
544  */
545 #define hw_spimaster_c0clk0 _usia_spimaster_c0clk, usi0
546 
547 
548 /*******************************************************************************
549  * *
550  * Analog Comparator *
551  * *
552  *******************************************************************************/
553 
554 /* Instance class, address
555  */
556 #include "../classes/acb_1.h"
557 #define hw_acmp0 _acb, 0
558 
559 /* Object hardware registers class, address, write mask, flags mask
560  */
561 #define hw_acmp0_csr _r8, 0x28, 0xDF, 0x10
562 
563 /* Object logical registers
564  */
565 #define hw_acmp0_acd _ob1, csr, 1, 7
566 #define hw_acmp0_acbg _ob1, csr, 1, 6
567 #define hw_acmp0_aco _ob1, csr, 1, 5
568 #define hw_acmp0_if _ob1, csr, 1, 4
569 #define hw_acmp0_ie _ob1, csr, 1, 3
570 #define hw_acmp0_acis _ob1, csr, 2, 0
571 
572 #define hw_acmp0_acme _xb1, adc0, srb, 1, 6
573 #define hw_acmp0_aden _xb1, adc0, sra, 1, 7
574 #define hw_acmp0_admux _xb1, adc0, admux, 4, 0
575 
576 
577 /*******************************************************************************
578  * *
579  * Analog-to-Digital Converter *
580  * *
581  *******************************************************************************/
582 
583 /* Object class, address
584  */
585 #include "../classes/adc_1.h"
586 #define hw_adc0 _adc, 0
587 
588 /* Object hardware registers class, address, write mask, flags mask
589  */
590 #define hw_adc0_admux _r8, 0x27, 0xFF, 0x00
591 #define hw_adc0_sra _r8, 0x26, 0xFF, 0x10
592 #define hw_adc0_adc _r16, 0x24, 0x0000, 0x0000
593 #define hw_adc0_adch _r8, 0x25, 0x00, 0x00
594 #define hw_adc0_srb _r8, 0x23, 0xE7, 0x00
595 
596 /* Object logical registers
597  */
598 #define hw_adc0_refs _ob2, admux, 2, 6, 0, admux, 1, 4, 2
599 #define hw_adc0_lar _ob1, admux, 1, 5
600 #define hw_adc0_mux _ob1, admux, 4, 0
601 
602 #define hw_adc0_en _ob1, sra, 1, 7
603 #define hw_adc0_sc _ob1, sra, 1, 6
604 #define hw_adc0_ate _ob1, sra, 1, 5
605 #define hw_adc0_if _ob1, sra, 1, 4
606 #define hw_adc0_ie _ob1, sra, 1, 3
607 #define hw_adc0_ps _ob1, sra, 3, 0
608 
609 #define hw_adc0_bin _ob1, srb, 1, 7
610 #define hw_adc0_ipr _ob1, srb, 1, 5
611 #define hw_adc0_ts _ob1, srb, 3, 0
612 
613 /* Analog inputs
614  */
615 #define hw_pin_adc0 _ioa, portb, 1, 5
616 #define hw_pin_adc1 _ioa, portb, 1, 2
617 #define hw_pin_adc2 _ioa, portb, 1, 4
618 #define hw_pin_adc3 _ioa, portb, 1, 3
619 #define hw_pin_ain1 _ioa, portb, 1, 1
620 #define hw_pin_ain0 _ioa, portb, 1, 0
621 
622 
623 /*******************************************************************************
624  * *
625  * EEPROM *
626  * *
627  *******************************************************************************/
628 
629 /* Class
630  */
631 #include "../classes/eea_1.h"
632 
633 /* Object class, address
634  */
635 #define hw_eeprom0 _eea, 0
636 
637 /* Class hardware registers class, address, write mask, flags mask
638  */
639 #define hw__eea_ar _r16, 0x3E, 0x01FF, 0x00
640 #define hw__eea_dr _r8, 0x3D, 0xFF, 0x00
641 #define hw__eea_cr _r8, 0x3C, 0x3F, 0x00
642 
643 /* Class logical registers
644  */
645 #define hw__eea_pm _cb1, cr, 2, 4
646 #define hw__eea_rie _cb1, cr, 1, 3
647 #define hw__eea_mpe _cb1, cr, 1, 2
648 #define hw__eea_pe _cb1, cr, 1, 1
649 #define hw__eea_re _cb1, cr, 1, 0
650 
651 
652 /*******************************************************************************
653  * *
654  * Flash memory *
655  * *
656  *******************************************************************************/
657 
658 /* Class
659  */
660 #include "../classes/fla_1.h"
661 
662 /* Object class, address
663  */
664 #define hw_flash0 _fla, 0
665 
666 /* Class hardware registers class, address, write mask, flags mask
667  */
668 #define hw__fla_csr _r8, 0x57, 0x3F, 0x00
669 
670 /* Class logical registers
671  */
672 #define hw__fla_sigrd _cb1, csr, 1, 5
673 #define hw__fla_rsig _cb1, csr, 1, 5 /* old name */
674 #define hw__fla_rwwsre _cb1, csr, 1, 4
675 #define hw__fla_ctpb _cb1, csr, 1, 4 /* old name */
676 #define hw__fla_blbset _cb1, csr, 1, 3
677 #define hw__fla_rflb _cb1, csr, 1, 3 /* old name */
678 #define hw__fla_pgwrt _cb1, csr, 1, 2
679 #define hw__fla_pgers _cb1, csr, 1, 1
680 #define hw__fla_spmen _cb1, csr, 1, 0
681 
682 
683 /*******************************************************************************
684  * *
685  * C O N T E X T *
686  * *
687  *******************************************************************************/
688 
689 
690 #if !defined __ASSEMBLER__
691 
692 /* This structure is instanciated by hwa( begin ) or hwa( begin, reset ) and
693  * used by all HWA asynchronous instructions to bufferize hardware accesses.
694  */
695 typedef struct {
696  uint8_t commit ;
697 
698  hwa_shared_t shared ;
699 
700  hwa_corea_t core0 ;
701  hwa_gpa_t portb ;
702  hwa_pxa_t pcic0 ;
703  hwa_wda_t watchdog0 ;
704  hwa_cta_t counter0 ;
705  hwa_psb_t prescaler1 ;
706  hwa_ctb_t counter1 ;
707  hwa_usia_t usi0 ;
708  hwa_acb_t acmp0 ;
709  hwa_adc_t adc0 ;
710 } hwa_t ;
711 
712 #include "../hwa_2.h"
713 #include "../classes/c1_2.h"
714 #include "../classes/corea_2.h"
715 #include "../classes/wda_2.h"
716 #include "../classes/inta_2.h"
717 #include "../classes/ioa_2.h"
718 #include "../classes/gpa_2.h"
719 #include "../classes/pxa_2.h"
720 #include "../classes/psa_2.h"
721 #include "../classes/oca_2.h"
722 #include "../classes/cta_2.h"
723 #include "../classes/ctb_2.h"
724 #include "../classes/ocb_2.h"
725 #include "../classes/psb_2.h"
726 #include "../classes/dtga_2.h"
727 #include "../classes/usia_2.h"
728 #include "../classes/adc_2.h"
729 #include "../classes/acb_2.h"
730 #include "../classes/eea_2.h"
731 #include "../classes/fla_2.h"
732 
733 
734 HW_INLINE void _hwa_setup_context( hwa_t *hwa )
735 {
736  _hwa_setup_r( shared, gimsk );
737  _hwa_setup_r( shared, gifr );
738  _hwa_setup_r( shared, prr );
739  _hwa_setup_r( shared, gtccr );
740  _hwa_setup_r( shared, timsk );
741  _hwa_setup_r( shared, tifr );
742  _hwa_setup_r( shared, did );
743 
744  _hwa_setup_o( core0 );
745 
746  _hwa_setup_o( portb );
747  _hwa_setup_o( pcic0 );
748  _hwa_setup_o( watchdog0 );
749  _hwa_setup_o( counter0 );
750  _hwa_setup_o( prescaler1 );
751  _hwa_setup_o( counter1 );
752 
753  _hwa_setup_o( usi0 );
754  _hwa_setup_o( acmp0 );
755  _hwa_setup_o( adc0 );
756 }
757 
758 HW_INLINE void _hwa_init_context( hwa_t *hwa )
759 {
760  _hwa_init_r( shared, gimsk, 0 );
761  _hwa_init_r( shared, gifr, 0 );
762  _hwa_init_r( shared, prr, 0 );
763  _hwa_init_r( shared, gtccr, 0 );
764  _hwa_init_r( shared, timsk, 0 );
765  _hwa_init_r( shared, tifr, 0 );
766  _hwa_init_r( shared, did, 0 );
767 
768  _hwa_init_o( core0 );
769  _hwa_init_o( portb );
770  _hwa_init_o( pcic0 );
771  _hwa_init_o( watchdog0 );
772  _hwa_init_o( counter0 );
773  _hwa_init_o( prescaler1 );
774  _hwa_init_o( counter1 );
775  _hwa_init_o( usi0 );
776  _hwa_init_o( acmp0 );
777  _hwa_init_o( adc0 );
778 }
779 
780 HW_INLINE void _hwa_commit_context( hwa_t *hwa )
781 {
782  _hwa_solve_o( counter0 );
783  _hwa_solve_o( counter1 );
784 
785  _hwa_commit_r( shared, gimsk );
786  _hwa_commit_r( shared, gifr );
787  _hwa_commit_o( core0 );
788  _hwa_commit_r( shared, prr );
789 
790  _hwa_commit_o( watchdog0 );
791  _hwa_commit_o( pcic0 );
792  _hwa_commit_o( portb );
793 
794  _hwa_commit_r( shared, gtccr );
795  _hwa_commit_o( counter0 );
796  _hwa_commit_r( shared, timsk );
797  _hwa_commit_r( shared, tifr );
798 
799  _hwa_commit_o( prescaler1 );
800  _hwa_commit_o( counter1 );
801  _hwa_commit_o( usi0 );
802  _hwa_commit_o( acmp0 );
803  _hwa_commit_o( adc0 );
804  _hwa_commit_r( shared, did );
805 }
806 
807 #endif /* !defined __ASSEMBLER__ */
_hwa_init_r
#define _hwa_init_r(o, r, v)
Initialize an HWA register of an object with its reset value.
Definition: hwa_2.h:369
_hwa_init_o
#define _hwa_init_o(o)
Initialize the HWA context registers of an object with their reset value.
Definition: hwa_2.h:331
_hwa_solve_o
#define _hwa_solve_o(o)
Solve the configuration of an object.
Definition: hwa_2.h:340
hwa
#define hwa(...)
hwa( action, object [,...] ) stores an action for an object into a HWA context.
Definition: hwa_macros.h:552
_hwa_setup_r
#define _hwa_setup_r(o, r)
Create a HWA register.
Definition: hwa_2.h:359
_hwa_commit_r
#define _hwa_commit_r(o, r)
Commit one object hardware register.
Definition: hwa_2.h:379
_hwa_commit_o
#define _hwa_commit_o(o)
Commit the registers of an object.
Definition: hwa_2.h:349
_hwa_setup_o
#define _hwa_setup_o(o)
Initialize the HWA context registers addresses of an object.
Definition: hwa_2.h:322