Class _dtga: dead time generator

_dtga objects are dead time generators.

They are used in:

• ATtiny25/45/85 : dtg1

Actions

configure:

The same clock prescaler is used for the 4 units. delay_h and delay_l are the number of prescaled clock units before the assertion of the corresponding output:

hw|hwa( configure, (counter0,compare0,dtg),
 
      [ prescaler,  1 | 2 | 4 | 8, ]  // default is `1`
 
      [ delay_h, 0..15, ]             // default is `0`
 
      [ delay_l, 0..15, ] );          // default is `0`

hw|hwa( write, (counter0,compare0,dtg,prescaler), 4 );

hw( configure, (counter0,dtg0),
 
  [ prescaler,  1 | 2 | 4 | 8, ]      // default is `1`
 
  [ compare0_h, 0..15, ]              // default is `0`
 
  [ compare0_l, 0..15, ]              // default is `0`
 
  [ compare1_h, 0..15, ]              // default is `0`
 
  [ compare1_l, 0..15  ] );           // default is `0`

Internals

Class _dtga objects hold the following hardware registers:

• dtps : clock prescaler
• dta : dead time register a
• dtb : dead time register b

that hold the following logical registers:

• psc : clock prescaler
• compare0_h : delay for output pin of compare unit 0
• compare0_l : delay for complementary output pin of compare unit 0
• compare1_h : delay for output pin of compare unit 1
• compare1_l : delay for complementary output pin of compare unit 1