HWA
Bare metal programming with style
atmegax8.h
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1 
2 /* This file is part of the HWA project.
3  * Copyright (c) 2012,2015 Christophe Duparquet.
4  * All rights reserved. Read LICENSE.TXT for details.
5  */
6 
70 /* Litterature:
71  * * AVR532: Migration from ATmega48/88/168 to ATmega48A/88A/168A
72  * * AVR512: Migration from ATmega48/88/168 to ATmega48P/88P/168P
73  * * AVR528: Migrating from ATmega48P/88P/168P to ATmega48PA/88PA/168PA
74  */
75 
87 #define HW_DEVICE_ATMEGAX8
88 
92 #define HW_DEVICE_RAM_START 0x0100
93 
98 #include "../hwa_1.h"
99 #include "atmegax8_fuses.h"
100 
101 #define _hw_isr_int0 , 1
102 #define _hw_isr_int1 , 2
103 #define _hw_isr_pcic0 , 3
104 #define _hw_isr_pcic1 , 4
105 #define _hw_isr_pcic2 , 5
106 #define _hw_isr_watchdog0 , 6
107 #define _hw_isr_counter2_compare0 , 7
108 #define _hw_isr_counter2_compare1 , 8
109 #define _hw_isr_counter2_overflow , 9
110 #define _hw_isr_counter2 , 9
111 #define _hw_isr_counter1_capture0 , 10
112 #define _hw_isr_counter1_compare0 , 11
113 #define _hw_isr_counter1_compare1 , 12
114 #define _hw_isr_counter1_overflow , 13
115 #define _hw_isr_counter1 , 13
116 #define _hw_isr_counter0_compare0 , 14
117 #define _hw_isr_counter0_compare1 , 15
118 #define _hw_isr_counter0_overflow , 16
119 #define _hw_isr_counter0 , 16
120 #define _hw_isr_spi0 , 17
121 #define _hw_isr_spi0_txc , 17
122 #define _hw_isr_uart0_rxc , 18
123 #define _hw_isr_uart0_txqnf , 19
124 #define _hw_isr_uart0_txc , 20
125 #define _hw_isr_adc0 , 21
126 #define _hw_isr_eeprom0 , 22
127 #define _hw_isr_eeprom0_ready , 22
128 #define _hw_isr_acmp0 , 23
129 #define _hw_isr_twi0 , 24
130 #define _hw_isr_flash0 , 25
131 
132 #define hw_int0_irq _irq, 1, int0, ie, if
133 #define hw_int1_irq _irq, 2, int1, ie, if
134 #define hw_pcic0_irq _irq, 3, pcic0, ie, if
135 #define hw_pcic1_irq _irq, 4, pcic1, ie, if
136 #define hw_pcic2_irq _irq, 5, pcic2, ie, if
137 #define hw_watchdog0_irq _irq, 6, watchdog0, ie, if
138 #define hw_counter2_irq_compare0 _irq, 7, counter2, ocie0, ocif0
139 #define hw_counter2_compare0_irq _irq, 7, counter2, ocie0, ocif0
140 #define hw_counter2_irq_compare1 _irq, 8, counter2, ocie1, ocif1
141 #define hw_counter2_compare1_irq _irq, 8, counter2, ocie1, ocif1
142 #define hw_counter2_irq_overflow _irq, 9, counter2, ie, if
143 #define hw_counter2_irq _irq, 9, counter2, ie, if
144 #define hw_counter1_irq_capture0 _irq, 10, counter1, icie0, icif0
145 #define hw_counter1_capture0_irq _irq, 10, counter1, icie0, icif0
146 #define hw_counter1_irq_compare0 _irq, 11, counter1, ocie0, ocif0
147 #define hw_counter1_compare0_irq _irq, 11, counter1, ocie0, ocif0
148 #define hw_counter1_irq_compare1 _irq, 12, counter1, ocie1, ocif1
149 #define hw_counter1_compare1_irq _irq, 12, counter1, ocie1, ocif1
150 #define hw_counter1_irq_overflow _irq, 13, counter1, ie, if
151 #define hw_counter1_irq _irq, 13, counter1, ie, if
152 #define hw_counter0_irq_compare0 _irq, 14, counter0, ocie0, ocif0
153 #define hw_counter0_compare0_irq _irq, 14, counter0, ocie0, ocif0
154 #define hw_counter0_irq_compare1 _irq, 15, counter0, ocie1, ocif1
155 #define hw_counter0_compare1_irq _irq, 15, counter0, ocie1, ocif1
156 #define hw_counter0_irq_overflow _irq, 16, counter0, ie, if
157 #define hw_counter0_irq _irq, 16, counter0, ie, if
158 #define hw_spi0_irq _irq, 17, spi0, ie, if
159 #define hw_spi0_irq_txc _irq, 17, spi0, ie, if
160 #define hw_uart0_irq _irq, , , , /* FIXME: should create a class for concatenation */
161 #define hw_uart0_irq_rxc _irq, 18, uart0, ierxc, ifrxc
162 #define hw_uart0_irq_txqnf _irq, 19, uart0, ietxqe, iftxqnf
163 #define hw_uart0_irq_txc _irq, 20, uart0, ietxc, iftxc
164 #define hw_adc0_irq _irq, 21, adc0, ie, if
165 #define hw_eeprom0_irq _irq, 22, eeprom0, ie, /* no irq flag */
166 #define hw_eeprom0_irq_ready _irq, 22, eeprom0, ie,
167 #define hw_acmp0_irq _irq, 23, acmp0, ie, if
168 #define hw_twi0_irq _irq, 24, twi0, ie, if
169 #define hw_flash0_irq _irq, 25, flash0, ie, if
170 
171 
172 
173 /*******************************************************************************
174  * *
175  * Peripherals *
176  * *
177  *******************************************************************************/
178 
179 
180 /*******************************************************************************
181  * *
182  * Shared registers *
183  * *
184  * This is an object used to gather hardware registers shared *
185  * by several objects *
186  * *
187  *******************************************************************************/
188 
189 /* Object class, address
190  */
191 #define hw_class__shared
192 #define hw_shared _shared, 0
193 
194 /* Object hardware registers class, address, write mask, flags mask
195  */
196 #define hw_shared_did1 _r8, 0x7F, 0x03, 0x00 /* DID for AIN0/AIN1 */
197 #define hw_shared_did0 _r8, 0x7E, 0x3F, 0x00 /* DID for PORTC */
198 #define hw_shared_eicr _r8, 0x69, 0x0F, 0x00
199 #define hw_shared_pcicr _r8, 0x68, 0x07, 0x00
200 #define hw_shared_prr _r8, 0x64, 0xEF, 0x00
201 #define hw_shared_gpior2 _r8, 0x4B, 0xFF, 0x00
202 #define hw_shared_gpior1 _r8, 0x4A, 0xFF, 0x00
203 #define hw_shared_gtccr _r8, 0x43, 0x83, 0x00
204 #define hw_shared_gpior0 _r8, 0x3E, 0xFF, 0x00
205 #define hw_shared_eimsk _r8, 0x3D, 0x03, 0x00
206 #define hw_shared_eifr _r8, 0x3C, 0x03, 0x03
207 #define hw_shared_pcifr _r8, 0x3B, 0x07, 0x07
208 
209 #if !defined __ASSEMBLER__
210 /*
211  * HWA context
212  */
213 typedef struct {
214 
215  /* Hardware registers
216  */
217  hwa_r8_t eimsk ;
218  hwa_r8_t eicr ;
219  hwa_r8_t eifr ;
220  hwa_r8_t gtccr ;
221  hwa_r8_t prr ;
222  hwa_r8_t did1 ;
223  hwa_r8_t did0 ;
224  hwa_r8_t pcicr ;
225  hwa_r8_t pcifr ;
226 } hwa_shared_t ;
227 #endif
228 
229 
230 /*******************************************************************************
231  * *
232  * Ports and pins *
233  * *
234  *******************************************************************************/
235 
236 /* Objects class, address
237  */
238 #include "../classes/gpa_1.h"
239 #include "../classes/ioa_1.h"
240 
241 #define hw_portb _gpa, 0x23
242 #define hw_portc _gpa, 0x26
243 #define hw_portd _gpa, 0x29
244 
245 /* Not-connected pins
246  */
247 #if !defined HW_NC_PB0
248 # define HW_NC_PB0 0
249 #endif
250 
251 #if !defined HW_NC_PB6
252 # define HW_NC_PB6 0
253 #endif
254 
255 #if !defined HW_NC_PB7
256 # define HW_NC_PB7 0
257 #endif
258 
259 #if !defined HW_NC_PC6
260 # define HW_NC_PC6 0
261 #endif
262 
263 #define HW_PORTB_NCMSK HW_NC_PB7*0x80 + HW_NC_PB6*0x40 + HW_NC_PB0
264 
265 #if HW_PORTB_NCMSK
266 # define _hw_portb_ncmsk , HW_PORTB_NCMSK
267 #endif
268 
269 #define HW_PORTC_NCMSK HW_NC_PC6*0x40
270 
271 #if HW_PORTC_NCMSK
272 # define _hw_portc_ncmsk , HW_PORTC_NCMSK
273 #endif
274 
275 /* Digital input disable bits for analog input pins
276  */
277 #define hw_portc_1_0_did _xb1, shared, did0, 1, 0 /* ADC0 */
278 #define hw_portc_1_1_did _xb1, shared, did0, 1, 1 /* ADC1 */
279 #define hw_portc_1_2_did _xb1, shared, did0, 1, 2 /* ADC2 */
280 #define hw_portc_1_3_did _xb1, shared, did0, 1, 3 /* ADC3 */
281 #define hw_portc_1_4_did _xb1, shared, did0, 1, 4 /* ADC4 */
282 #define hw_portc_1_5_did _xb1, shared, did0, 1, 5 /* ADC5 */
283 
284 #define hw_portd_1_6_did _xb1, shared, did1, 1, 0 /* AIN0 */
285 #define hw_portd_1_7_did _xb1, shared, did1, 1, 1 /* AIN1 */
286 
287 /* /\* TODO: handle these special pins differently. */
288 /* *\/ */
289 /* #define hw_pc6a _ioa, portc, 1, 8 */
290 /* #define hw_pc7a _ioa, portc, 1, 9 */
291 
292 /* Relatives
293  */
294 #define hw_portb_pcic pcic0
295 #define hw_portc_pcic pcic1
296 #define hw_portd_pcic pcic2
297 
298 /* Canonical pin names
299  */
300 #define hw_pin_sck _ioa, portb, 1, 5
301 #define hw_pin_miso _ioa, portb, 1, 4
302 #define hw_pin_mosi _ioa, portb, 1, 3
303 #define hw_pin_ss _ioa, portb, 1, 2
304 
305 #define hw_pin_adc0 _ioa, portc, 1, 0
306 #define hw_pin_adc1 _ioa, portc, 1, 1
307 #define hw_pin_adc2 _ioa, portc, 1, 2
308 #define hw_pin_adc3 _ioa, portc, 1, 3
309 #define hw_pin_adc4 _ioa, portc, 1, 4
310 #define hw_pin_adc5 _ioa, portc, 1, 5
311 #define hw_pin_adc6 _ioa, portc, 1, 6 /* a */
312 #define hw_pin_adc7 _ioa, portc, 1, 7 /* a */
313 
314 #define hw_pin_ain1 _ioa, portd, 1, 7
315 #define hw_pin_ain0 _ioa, portd, 1, 6
316 
317 #define hw_pin_scl _ioa, portc, 1, 5
318 #define hw_pin_sda _ioa, portc, 1, 4
319 
320 #define hw_pin_txd _ioa, portd, 1, 1
321 #define hw_pin_rxd _ioa, portd, 1, 0
322 
323 #if defined HW_DEVICE_PACKAGE_28P
324 #
325 # define hw_pin_1 _ioa, portc, 1, 6
326 # define hw_pin_2 _ioa, portd, 1, 0
327 # define hw_pin_3 _ioa, portd, 1, 1
328 # define hw_pin_4 _ioa, portd, 1, 2
329 # define hw_pin_5 _ioa, portd, 1, 3
330 # define hw_pin_6 _ioa, portd, 1, 4
331 # define hw_pin_9 _ioa, portb, 1, 6
332 # define hw_pin_10 _ioa, portb, 1, 7
333 # define hw_pin_11 _ioa, portd, 1, 5
334 # define hw_pin_12 _ioa, portd, 1, 6
335 # define hw_pin_13 _ioa, portd, 1, 7
336 # define hw_pin_14 _ioa, portb, 1, 0
337 # define hw_pin_15 _ioa, portb, 1, 1
338 # define hw_pin_16 _ioa, portb, 1, 2
339 # define hw_pin_17 _ioa, portb, 1, 3
340 # define hw_pin_18 _ioa, portb, 1, 4
341 # define hw_pin_19 _ioa, portb, 1, 5
342 # define hw_pin_23 _ioa, portc, 1, 0
343 # define hw_pin_24 _ioa, portc, 1, 1
344 # define hw_pin_25 _ioa, portc, 1, 2
345 # define hw_pin_26 _ioa, portc, 1, 3
346 # define hw_pin_27 _ioa, portc, 1, 4
347 # define hw_pin_28 _ioa, portc, 1, 5
348 #
349 #elif defined HW_DEVICE_PACKAGE_28Q
350 #
351 # define hw_pin_1 _ioa, portd, 1, 3
352 # define hw_pin_2 _ioa, portd, 1, 4
353 /* # define _hw_pin_3 , pin_ */
354 /* # define _hw_pin_4 , pin_ */
355 # define hw_pin_5 _ioa, portb, 1, 6
356 # define hw_pin_6 _ioa, portb, 1, 7
357 # define hw_pin_7 _ioa, portd, 1, 5
358 # define hw_pin_8 _ioa, portd, 1, 6
359 # define hw_pin_9 _ioa, portd, 1, 7
360 # define hw_pin_10 _ioa, portb, 1, 0
361 # define hw_pin_11 _ioa, portb, 1, 1
362 # define hw_pin_12 _ioa, portb, 1, 2
363 # define hw_pin_13 _ioa, portb, 1, 3
364 # define hw_pin_14 _ioa, portb, 1, 4
365 # define hw_pin_15 _ioa, portb, 1, 5
366 /* # define _hw_pin_16 , pin_ */
367 /* # define _hw_pin_17 , pin_ */
368 /* # define _hw_pin_18 , pin_ */
369 # define hw_pin_19 _ioa, portc, 1, 0
370 # define hw_pin_20 _ioa, portc, 1, 1
371 # define hw_pin_21 _ioa, portc, 1, 2
372 # define hw_pin_22 _ioa, portc, 1, 3
373 # define hw_pin_23 _ioa, portc, 1, 4
374 # define hw_pin_24 _ioa, portc, 1, 5
375 # define hw_pin_25 _ioa, portc, 1, 6
376 # define hw_pin_26 _ioa, portd, 1, 0
377 # define hw_pin_27 _ioa, portd, 1, 1
378 # define hw_pin_28 _ioa, portd, 1, 2
379 #
380 #elif defined HW_DEVICE_PACKAGE_32Q
381 #
382 # define hw_pin_1 _ioa, portd, 1, 3
383 # define hw_pin_2 _ioa, portd, 1, 4
384 # define hw_pin_7 _ioa, portb, 1, 6
385 # define hw_pin_8 _ioa, portb, 1, 7
386 # define hw_pin_9 _ioa, portd, 1, 5
387 # define hw_pin_10 _ioa, portd, 1, 6
388 # define hw_pin_11 _ioa, portd, 1, 7
389 # define hw_pin_12 _ioa, portb, 1, 0
390 # define hw_pin_13 _ioa, portb, 1, 1
391 # define hw_pin_14 _ioa, portb, 1, 2
392 # define hw_pin_15 _ioa, portb, 1, 3
393 # define hw_pin_16 _ioa, portb, 1, 4
394 # define hw_pin_17 _ioa, portb, 1, 5
395 /* # define _hw_pin_19 _ioa, portc, 1, 6a */
396 /* # define _hw_pin_22 _ioa, portc, 1, 7a */
397 # define hw_pin_23 _ioa, portc, 1, 0
398 # define hw_pin_24 _ioa, portc, 1, 1
399 # define hw_pin_25 _ioa, portc, 1, 2
400 # define hw_pin_26 _ioa, portc, 1, 3
401 # define hw_pin_27 _ioa, portc, 1, 4
402 # define hw_pin_28 _ioa, portc, 1, 5
403 # define hw_pin_29 _ioa, portc, 1, 6
404 # define hw_pin_30 _ioa, portd, 1, 0
405 # define hw_pin_31 _ioa, portd, 1, 1
406 # define hw_pin_32 _ioa, portd, 1, 2
407 #
408 #endif
409 
410 
411 /* Special pins
412  * These definitions make the (pin,...) notation work and give
413  * them an address.
414  */
415 #define hw_pin_aref _pin, 0x1001
416 #define hw_pin_avcc _pin, 0x1002
417 
418 
419 /*******************************************************************************
420  * *
421  * Core *
422  * *
423  *******************************************************************************/
424 
425 /* Object class, address
426  */
427 #include "../classes/coreb_1.h"
428 #define hw_core0 _coreb, 0
429 
430 /* Object hardware registers class, address, write mask, flags mask
431  */
432 #define hw_core0_osccal _r8, 0x66, 0xFF, 0x00
433 #define hw_core0_sreg _r8, 0x5F, 0xFF, 0x00
434 #define hw_core0_sph _r8, 0x5E, 0x03, 0x00
435 #define hw_core0_spl _r8, 0x5D, 0xFF, 0x00
436 #define hw_core0_mcucr _r8, 0x55, 0x73, 0x00
437 #define hw_core0_mcusr _r8, 0x54, 0x0F, 0x00
438 #define hw_core0_smcr _r8, 0x53, 0x0F, 0x00
439 
440 /* Object logical registers
441  */
442 #define hw_core0_bods _ob1, mcucr, 1, 6
443 #define hw_core0_bodse _ob1, mcucr, 1, 5
444 #define hw_core0_pud _ob1, mcucr, 1, 4
445 #define hw_core0_ivsel _ob1, mcucr, 1, 1
446 #define hw_core0_ivce _ob1, mcucr, 1, 0
447 
448 #define hw_core0_wdrf _ob1, mcusr, 1, 3
449 #define hw_core0_borf _ob1, mcusr, 1, 2
450 #define hw_core0_extrf _ob1, mcusr, 1, 1
451 #define hw_core0_porf _ob1, mcusr, 1, 0
452 #define hw_core0_allrf _ob1, mcusr, 4, 0 /* convenient */
453 
454 #define hw_core0_sm _ob1, smcr, 3, 1
455 #define hw_core0_se _ob1, smcr, 1, 0
456 
457 
458 /*******************************************************************************
459  * *
460  * External interrupt controllers *
461  * *
462  *******************************************************************************/
463 
464 #include "../classes/inta_1.h"
465 
466 /* Object class, address
467  */
468 #define hw_int0 _inta, 0
469 
470 /* Object logical registers
471  */
472 #define hw_int0_sc _xb1, shared, eicr, 2, 0
473 #define hw_int0_ie _xb1, shared, eimsk, 1, 0
474 #define hw_int0_if _xb1, shared, eifr, 1, 0
475 
476 /* Object class, address
477  */
478 #define hw_int1 _inta, 0
479 
480 /* Object logical registers
481  */
482 #define hw_int1_sc _xb1, shared, eicr, 2, 2
483 #define hw_int1_ie _xb1, shared, eimsk, 1, 1
484 #define hw_int1_if _xb1, shared, eifr, 1, 1
485 
486 
487 /*******************************************************************************
488  * *
489  * Pin-change interrupt controller *
490  * *
491  *******************************************************************************/
492 
493 #include "../classes/pxa_1.h"
494 
495 /* Object class, address
496  */
497 #define hw_pcic0 _pxa, 0
498 
499 /* Object hardware registers class, address, write mask, flags mask
500  */
501 #define hw_pcic0_msk _r8, 0x6B, 0xFF, 0x00
502 
503 /* Object logical registers
504  */
505 #define hw_pcic0_ie _xb1, shared, pcicr, 1, 0
506 #define hw_pcic0_if _xb1, shared, pcifr, 1, 0
507 
508 /* Object class, address
509  */
510 #define hw_pcic1 _pxa, 0
511 
512 /* Object hardware registers class, address, write mask, flags mask
513  */
514 #define hw_pcic1_msk _r8, 0x6C, 0x7F, 0x00
515 
516 /* Object logical registers
517  */
518 #define hw_pcic1_ie _xb1, shared, pcicr, 1, 1
519 #define hw_pcic1_if _xb1, shared, pcifr, 1, 1
520 
521 /* Object class, address
522  */
523 #define hw_pcic2 _pxa, 0
524 
525 /* Object hardware registers class, address, write mask, flags mask
526  */
527 #define hw_pcic2_msk _r8, 0x6D, 0xFF, 0x00
528 
529 /* Object logical registers
530  */
531 #define hw_pcic2_ie _xb1, shared, pcicr, 1, 2
532 #define hw_pcic2_if _xb1, shared, pcifr, 1, 2
533 
534 
535 /*******************************************************************************
536  * *
537  * hw_watchdog0: watchdog *
538  * *
539  *******************************************************************************/
540 
541 #include "../classes/wdb_1.h"
542 
543 /* Object class, address
544  */
545 #define hw_watchdog0 _wdb, 0
546 
547 /* Class hardware registers class, address, write mask, flags mask
548  */
549 #define hw__wdb_csr _r8, 0x60, 0xFF, 0x80
550 
551 /* Class logical registers
552  */
553 #define hw__wdb_wdrf _xb1, core0, mcusr, 1, 3
554 
555 
556 /*******************************************************************************
557  * *
558  * Counter 0/1 prescaler *
559  * *
560  *******************************************************************************/
561 
562 #include "../classes/psa_1.h"
563 
564 /* Object class, address
565  */
566 #define hw_prescaler0 _psa, 0
567 
568 /* Object logical registers
569  */
570 #define hw_prescaler0_tsm _xb1, shared, gtccr, 1, 7
571 #define hw_prescaler0_psr _xb1, shared, gtccr, 1, 0
572 
573 /* This is a convenient logical register definition for stopping the prescaler
574  */
575 #define hw_prescaler0_tsmpsr _xb2, shared, gtccr, 1, 7, 1, gtccr, 1, 0, 0
576 
577 
578 /*******************************************************************************
579  * *
580  * Counter 0 *
581  * *
582  *******************************************************************************/
583 
584 #include "../classes/oca_1.h"
585 #include "../classes/cta_1.h"
586 
587 /* Object class, address
588  */
589 #define hw_counter0 _cta, 0
590 
591 /* Hardware registers class, address, write mask, flags mask
592  */
593 #define hw_counter0_imsk _r8, 0x6E, 0x07, 0x00
594 #define hw_counter0_ocr1 _r8, 0x48, 0xFF, 0x00 /* OCR0B */
595 #define hw_counter0_ocr0 _r8, 0x47, 0xFF, 0x00 /* OCR0A */
596 #define hw_counter0_ccra _r8, 0x44, 0xF3, 0x00
597 #define hw_counter0_ccrb _r8, 0x45, 0xCF, 0x00
598 #define hw_counter0_count _r8, 0x46, 0xFF, 0x00
599 #define hw_counter0_ifr _r8, 0x35, 0x07, 0x07
600 
601 /* Logical registers
602  */
603 #define hw_counter0_com0 _ob1, ccra, 2, 6
604 #define hw_counter0_com1 _ob1, ccra, 2, 4
605 #define hw_counter0_wgm _ob2, ccra, 2, 0, 0, ccrb, 1, 3, 2
606 
607 #define hw_counter0_foc0 _ob1, ccrb, 1, 7
608 #define hw_counter0_foc1 _ob1, ccrb, 1, 6
609 #define hw_counter0_cs _ob1, ccrb, 3, 0
610 
611 #define hw_counter0_ocie1 _ob1, imsk, 1, 2
612 #define hw_counter0_ocie0 _ob1, imsk, 1, 1
613 #define hw_counter0_ie _ob1, imsk, 1, 0
614 
615 #define hw_counter0_ocif1 _ob1, ifr, 1, 2
616 #define hw_counter0_ocif0 _ob1, ifr, 1, 1
617 #define hw_counter0_if _ob1, ifr, 1, 0
618 
619 #define hw_counter0_prr _xb1, shared, prr, 1, 5
620 
621 /* Relatives
622  */
623 #define hw_counter0_prescaler0 prescaler0
624 #define hw_counter0_prescaler prescaler0
625 
626 #define hw_counter0_compare0 _oca, counter0, 0
627 #define hw_counter0_compare0_pin _ioa, portd, 1, 6
628 #define hw_counter0_compare0_counter counter0
629 
630 #define hw_counter0_compare1 _oca, counter0, 1
631 #define hw_counter0_compare1_pin _ioa, portd, 1, 5
632 #define hw_counter0_compare1_counter counter0
633 
634 
635 /*******************************************************************************
636  * *
637  * Counter 1 *
638  * *
639  *******************************************************************************/
640 
641 #include "../classes/occ_1.h"
642 #include "../classes/ica_1.h"
643 #include "../classes/ctd_1.h"
644 
645 /* Object class, address
646  */
647 #define hw_counter1 _ctd, 0
648 
649 /* Hardware registers class, address, write mask, flags mask
650  */
651 #define hw_counter1_ocr1 _r16, 0x8A, 0xFFFF, 0x0000 /* OCR1B */
652 #define hw_counter1_ocr0 _r16, 0x88, 0xFFFF, 0x0000 /* OCR1A */
653 #define hw_counter1_icr0 _r16, 0x86, 0xFFFF, 0x0000 /* ICR1 */
654 #define hw_counter1_count _r16, 0x84, 0xFFFF, 0x0000
655 #define hw_counter1_ccrc _r8, 0x82, 0xC0, 0x00
656 #define hw_counter1_ccrb _r8, 0x81, 0xDF, 0x00
657 #define hw_counter1_ccra _r8, 0x80, 0xF3, 0x00
658 #define hw_counter1_imsk _r8, 0x6F, 0x27, 0x00
659 #define hw_counter1_ifr _r8, 0x36, 0x27, 0x27
660 
661 /* Logical registers
662  */
663 #define hw_counter1_foc0 _ob1, ccrc, 1, 7
664 #define hw_counter1_foc1 _ob1, ccrc, 1, 6
665 
666 #define hw_counter1_icnc _ob1, ccrb, 1, 7
667 #define hw_counter1_ices _ob1, ccrb, 1, 6
668 #define hw_counter1_cs _ob1, ccrb, 3, 0
669 #define hw_counter1_wgm _ob2, ccrb, 2, 3, 2, ccra, 2, 0, 0
670 
671 #define hw_counter1_com0 _ob1, ccra, 2, 6
672 #define hw_counter1_com1 _ob1, ccra, 2, 4
673 
674 #define hw_counter1_icie0 _ob1, imsk, 1, 5
675 #define hw_counter1_ocie1 _ob1, imsk, 1, 2
676 #define hw_counter1_ocie0 _ob1, imsk, 1, 1
677 #define hw_counter1_ie _ob1, imsk, 1, 0
678 
679 #define hw_counter1_icif0 _ob1, ifr, 1, 5
680 #define hw_counter1_ocif1 _ob1, ifr, 1, 2
681 #define hw_counter1_ocif0 _ob1, ifr, 1, 1
682 #define hw_counter1_if _ob1, ifr, 1, 0
683 
684 #define hw_counter1_prr _xb1, shared, prr, 1, 3
685 
686 #define hw_counter1_acic _xb1, acmp0, csr, 1, 2
687 
688 /* Relatives
689  */
690 #define hw_counter1_prescaler0 prescaler0
691 #define hw_counter1_prescaler prescaler0
692 
693 #define hw_counter1_compare0 _occ, counter1, 0
694 #define hw_counter1_compare0_pin _ioa, portb, 1, 1
695 #define hw_counter1_compare0_counter counter1
696 
697 #define hw_counter1_compare1 _occ, counter1, 1
698 #define hw_counter1_compare1_pin _ioa, portb, 1, 2
699 #define hw_counter1_compare1_counter counter1
700 
701 #define hw_counter1_capture0 _ica, counter1, 0
702 #define hw_counter1_capture0_pin _ioa, portb, 1, 0
703 #define hw_counter1_capture0_counter counter1
704 
705 
706 /*******************************************************************************
707  * *
708  * prescaler2: counter2 prescaler *
709  * *
710  * prescaler0 and prescaler2 share the same tsm bit *
711  * *
712  *******************************************************************************/
713 
714 /* Instance class, address
715  */
716 #define hw_prescaler2 _psa, 0
717 
718 /* Object registers class, address, write mask, flags mask
719  */
720 #define hw_prescaler2_tsm _xb1, shared, gtccr, 1, 7
721 #define hw_prescaler2_psr _xb1, shared, gtccr, 1, 1
722 
723 /* This is a convenient logical register definition for stopping the prescaler
724  */
725 #define hw_prescaler2_tsmpsr _xb2, shared, gtccr, 1, 7, 1, gtccr, 1, 1, 0
726 
727 
728 /*******************************************************************************
729  * *
730  * Counter 2 *
731  * *
732  *******************************************************************************/
733 
734 #include "../classes/ctc_1.h" /* was ctb */
735 
736 /* Object class, address
737  */
738 #define hw_counter2 _ctc, 0
739 
740 /* Hardware registers class, address, write mask, flags mask
741  */
742 #define hw_counter2_assr _r8, 0xB6, 0x60, 0x00
743 #define hw_counter2_ocr1 _r8, 0xB4, 0xFF, 0x00 /* OCR2B */
744 #define hw_counter2_ocr0 _r8, 0xB3, 0xFF, 0x00 /* OCR2A */
745 #define hw_counter2_count _r8, 0xB2, 0xFF, 0x00
746 #define hw_counter2_ccrb _r8, 0xB1, 0xCF, 0x00
747 #define hw_counter2_ccra _r8, 0xB0, 0xF3, 0x00
748 #define hw_counter2_imsk _r8, 0x70, 0x07, 0x00
749 #define hw_counter2_ifr _r8, 0x37, 0x07, 0x07
750 
751 /* Logical registers
752  */
753 #define hw_counter2_com0 _ob1, ccra, 2, 6
754 #define hw_counter2_com1 _ob1, ccra, 2, 4
755 #define hw_counter2_wgm _ob2, ccra, 2, 0, 0, ccrb, 1, 3, 2
756 
757 #define hw_counter2_foc0 _ob1, ccrb, 1, 7
758 #define hw_counter2_foc1 _ob1, ccrb, 1, 6
759 #define hw_counter2_cs _ob1, ccrb, 3, 0
760 
761 #define hw_counter2_ocie1 _ob1, imsk, 1, 2
762 #define hw_counter2_ocie0 _ob1, imsk, 1, 1
763 #define hw_counter2_ie _ob1, imsk, 1, 0
764 
765 #define hw_counter2_ocif1 _ob1, ifr, 1, 2
766 #define hw_counter2_ocif0 _ob1, ifr, 1, 1
767 #define hw_counter2_if _ob1, ifr, 1, 0
768 
769 #define hw_counter2_prr _xb1, shared, prr, 1, 6
770 
771 /* Relatives
772  */
773 #define hw_counter2_prescaler0 prescaler2
774 #define hw_counter2_prescaler prescaler2
775 
776 #define hw_counter2_compare0 _oca, counter2, 0
777 #define hw_counter2_compare0_pin _ioa, portb, 1, 3
778 #define hw_counter2_compare0_counter counter2
779 
780 #define hw_counter2_compare1 _oca, counter2, 1
781 #define hw_counter2_compare1_pin _ioa, portd, 1, 3
782 #define hw_counter2_compare1_counter counter2
783 
784 
785 /*******************************************************************************
786  * *
787  * Serial Peripheral Interface *
788  * *
789  *******************************************************************************/
790 
791 #include "../classes/spia_1.h"
792 
793 /* Object class, address
794  */
795 #define hw_spi0 _spia, 0
796 
797 /* Object hardware registers class, address, write mask, flags mask
798  */
799 #define hw_spi0_dr _r8, 0x4E, 0xFF, 0x00
800 #define hw_spi0_sr _r8, 0x4D, 0xFF, 0x00
801 #define hw_spi0_cr _r8, 0x4C, 0xFF, 0x00
802 
803 /* Object logical registers
804  */
805 #define hw_spi0_ie _ob1, cr, 1, 7
806 #define hw_spi0_en _ob1, cr, 1, 6
807 #define hw_spi0_dord _ob1, cr, 1, 5
808 #define hw_spi0_mstr _ob1, cr, 1, 4
809 #define hw_spi0_cpol _ob1, cr, 1, 3
810 #define hw_spi0_cpha _ob1, cr, 1, 2
811 #define hw_spi0_mode _ob1, cr, 2, 2 /* convenient */
812 
813 #define hw_spi0_if _ob1, sr, 1, 7
814 #define hw_spi0_wpol _ob1, sr, 1, 6
815 
816 #define hw_spi0_xpr _ob2, sr, 1, 0, 2, cr, 2, 0, 0
817 
818 /* Relatives
819  */
820 #define hw_spi0_mosi _ioa, portb, 1, 3
821 #define hw_spi0_miso _ioa, portb, 1, 4
822 #define hw_spi0_sck _ioa, portb, 1, 5
823 #define hw_spi0_ss _ioa, portb, 1, 2
824 
825 
826 /*******************************************************************************
827  * *
828  * UART *
829  * *
830  *******************************************************************************/
831 
832 #include "../classes/uarta_1.h"
833 
834 /* Object
835  */
836 #define hw_uart0 _uarta, 0x00
837 
838 /* Class hardware registers class, address, write mask, flags mask
839  */
840 #define hw__uarta_dr _r8, 0xC6, 0xFF, 0x00
841 #define hw__uarta_ubrr _r16, 0xC4, 0x0FFF, 0x0000
842 #define hw__uarta_csrc _r8, 0xC2, 0xFF, 0x00
843 #define hw__uarta_csrb _r8, 0xC1, 0xFD, 0x00
844 #define hw__uarta_csra _r8, 0xC0, 0x43, 0x40
845 
846 /* Class logical registers
847  */
848 #define hw__uarta_brr _cb1, ubrr, 12, 0
849 
850 #define hw__uarta_ifrxc _cb1, csra, 1, 7
851 #define hw__uarta_iftxc _cb1, csra, 1, 6
852 #define hw__uarta_iftxqnf _cb1, csra, 1, 5
853 #define hw__uarta_fe _cb1, csra, 1, 4
854 #define hw__uarta_dor _cb1, csra, 1, 3
855 #define hw__uarta_pe _cb1, csra, 1, 2
856 #define hw__uarta_2x _cb1, csra, 1, 1
857 #define hw__uarta_mpcm _cb1, csra, 1, 0
858 
859 #define hw__uarta_ierxc _cb1, csrb, 1, 7
860 #define hw__uarta_ietxc _cb1, csrb, 1, 6
861 #define hw__uarta_ietxqnf _cb1, csrb, 1, 5
862 #define hw__uarta_rxen _cb1, csrb, 1, 4
863 #define hw__uarta_txen _cb1, csrb, 1, 3
864 #define hw__uarta_rxb8 _cb1, csrb, 1, 1
865 #define hw__uarta_txb8 _cb1, csrb, 1, 0
866 
867 #define hw__uarta_msel _cb1, csrc, 2, 6
868 #define hw__uarta_pm _cb1, csrc, 2, 4
869 #define hw__uarta_sbs _cb1, csrc, 1, 3
870 #define hw__uarta_cpol _cb1, csrc, 1, 0
871 
872 #define hw__uarta_csz _cb2, csrb, 1, 2, 2, csrc, 2, 1, 0
873 
874 /* Object logical registers
875  */
876 #define hw_uart0_prr _xb1, shared, prr, 1, 1
877 
878 
879 /*******************************************************************************
880  * *
881  * 2-wire interface *
882  * *
883  *******************************************************************************/
884 
885 #include "../classes/twia_1.h"
886 
887 /* Object
888  */
889 #define hw_twi0 _twia, 0xB8
890 
891 /* Class hardware registers class, address, write mask, flags mask
892  */
893 #define hw__twia_br _r8, 0x00, 0xFF, 0x00
894 #define hw__twia_cr _r8, 0x04, 0xF5, 0x80
895 #define hw__twia_sr _r8, 0x01, 0x03, 0x00
896 #define hw__twia_dr _r8, 0x03, 0xFF, 0x00
897 #define hw__twia_ar _r8, 0x02, 0xFF, 0x00
898 #define hw__twia_amr _r8, 0x05, 0xFE, 0x00
899 
900 /* Relatives
901  */
902 #define hw_twi0_scl _ioa, portc, 1, 5
903 #define hw_twi0_sda _ioa, portc, 1, 4
904 
905 
906 /*******************************************************************************
907  * *
908  * acmp0: analog comparator *
909  * *
910  *******************************************************************************/
911 
912 #include "../classes/aca_1.h"
913 
914 /* Object class, address
915  */
916 #define hw_acmp0 _aca, 0
917 
918 /* Class hardware registers class, address, write mask, flags mask
919  */
920 #define hw__aca_csr _r8, 0x50, 0xDF, 0x10
921 
922 /* Object hardware registers
923  * Required for _hw_counter1capture0_acic
924  */
925 #define hw_acmp0_csr _r8, 0x50, 0xDF, 0x10
926 
927 /* Object logical registers
928  */
929 #define hw_acmp0_acme _xb1, adc0, srb, 1, 6
930 #define hw_acmp0_aden _xb1, adc0, sra, 1, 7
931 #define hw_acmp0_admux _xb1, adc0, admux, 4, 0
932 
933 
934 /*******************************************************************************
935  * *
936  * Analog-to-Digital Converter *
937  * *
938  *******************************************************************************/
939 
940 #include "../classes/adb_1.h"
941 
942 /* Object class, address
943  */
944 #define hw_adc0 _adb, 0
945 
946 /* Class hardware registers class, address, write mask, flags mask
947  */
948 #define hw__adb_admux _r8, 0x7C, 0xEF, 0x00
949 #define hw__adb_sra _r8, 0x7A, 0xFF, 0x10
950 #define hw__adb_adc _r16, 0x78, 0x0000, 0x0000
951 #define hw__adb_adch _r8, 0x79, 0x00, 0x00
952 #define hw__adb_adcl _r8, 0x78, 0x00, 0x00
953 #define hw__adb_srb _r8, 0x7B, 0x47, 0x00
954 
955 /* Object hardware registers class, address, write mask, flags mask
956  *
957  * These are necessary for acmp0, and analog input pin configuration
958  * that needs access to the did register of the ADC object.
959  */
960 #define hw_adc0_admux _r8, 0x7C, 0xEF, 0x00
961 #define hw_adc0_sra _r8, 0x7A, 0xFF, 0x10
962 #define hw_adc0_srb _r8, 0x7B, 0x47, 0x00
963 
964 /* Class logical registers
965  */
966 #define hw__adb_refs _cb1, admux, 2, 6
967 #define hw__adb_lar _cb1, admux, 1, 5
968 #define hw__adb_mux _cb1, admux, 4, 0
969 
970 #define hw__adb_en _cb1, sra, 1, 7
971 #define hw__adb_sc _cb1, sra, 1, 6
972 #define hw__adb_ate _cb1, sra, 1, 5
973 #define hw__adb_if _cb1, sra, 1, 4
974 #define hw__adb_ie _cb1, sra, 1, 3
975 #define hw__adb_ps _cb1, sra, 3, 0
976 
977 #define hw__adb_me _cb1, srb, 1, 6
978 #define hw__adb_ts _cb1, srb, 3, 0
979 
980 /* Object logical registers
981  */
982 #define hw_adc0_prr _xb1, shared, prr, 1, 0
983 
984 
985 /*******************************************************************************
986  * *
987  * EEPROM memory *
988  * *
989  *******************************************************************************/
990 
991 #define hw_class__eea
992 
993 /* Object class, address
994  */
995 #define hw_eeprom0 _eea, 0
996 
997 /* Class hardware registers class, address, write mask, flags mask
998  */
999 #define hw__eea_arh _r8, 0x42, 0x03, 0x00
1000 #define hw__eea_arl _r8, 0x41, 0xFF, 0x00
1001 #define hw__eea_ar _r16, 0x41, 0x03FF, 0x00
1002 #define hw__eea_dr _r8, 0x40, 0xFF, 0x00
1003 #define hw__eea_cr _r8, 0x3F, 0x3F, 0x00
1004 
1005 /* Class logical registers
1006  */
1007 #define hw__eea_pm _cb1, cr, 2, 4
1008 #define hw__eea_rie _cb1, cr, 1, 3
1009 #define hw__eea_mpe _cb1, cr, 1, 2
1010 #define hw__eea_pe _cb1, cr, 1, 1
1011 #define hw__eea_re _cb1, cr, 1, 0
1012 
1013 
1014 /*******************************************************************************
1015  * *
1016  * Flash memory *
1017  * *
1018  *******************************************************************************/
1019 
1020 #define hw_class__fla
1021 
1022 /* Object class, address
1023  */
1024 #define hw_flash0 _fla, 0
1025 
1026 /* Class hardware registers class, address, write mask, flags mask
1027  */
1028 #define hw__fla_csr _r8, 0x57, 0xBF, 0x00
1029 
1030 /* Class logical registers
1031  */
1032 #define hw__fla_spmie _cb1, csr, 1, 7
1033 #define hw__fla_rwwsb _cb1, csr, 1, 6
1034 #define hw__fla_sigrd _cb1, csr, 1, 5
1035 #define hw__fla_rwwsre _cb1, csr, 1, 4
1036 #define hw__fla_blbset _cb1, csr, 1, 3
1037 #define hw__fla_pgwrt _cb1, csr, 1, 2
1038 #define hw__fla_pgers _cb1, csr, 1, 1
1039 #define hw__fla_spmen _cb1, csr, 1, 0
1040 
1041 
1042 /*******************************************************************************
1043  * *
1044  * HWA context *
1045  * *
1046  *******************************************************************************/
1047 
1048 
1049 #if !defined __ASSEMBLER__
1050 
1051 /* This structure is instanciated by hwa( begin ) or hwa( begin, reset ) and
1052  * used by all HWA asynchronous instructions to bufferize hardware accesses.
1053  */
1054 typedef struct {
1055  uint8_t commit ;
1057  hwa_shared_t shared ;
1058 
1059  hwa_coreb_t core0 ;
1060  hwa_gpa_t portb ;
1061  hwa_gpa_t portc ;
1062  hwa_gpa_t portd ;
1063  hwa_pxa_t pcic0 ;
1064  hwa_pxa_t pcic1 ;
1065  hwa_pxa_t pcic2 ;
1066  hwa_wdb_t watchdog0 ;
1067 
1068  hwa_cta_t counter0 ;
1069  /* hwa_oca_t counter0compare0 ; */
1070  /* hwa_oca_t counter0compare1 ; */
1071 
1072  hwa_ctd_t counter1 ;
1073  /* hwa_occ_t counter1compare0 ; */
1074  /* hwa_occ_t counter1compare1 ; */
1075  /* hwa_ica_t counter1capture0 ; */
1076 
1077  hwa_ctc_t counter2 ;
1078  /* hwa_oca_t counter2compare0 ; */
1079  /* hwa_oca_t counter2compare1 ; */
1080 
1081  hwa_spia_t spi0 ;
1082  hwa_uarta_t uart0 ;
1083  hwa_twia_t twi0 ;
1084  hwa_aca_t acmp0 ;
1085  hwa_adb_t adc0 ;
1086 } hwa_t ;
1087 
1088 
1089 #include "../hwa_2.h"
1090 #include "../classes/c1_2.h"
1091 #include "../classes/ioa_2.h"
1092 #include "../classes/gpa_2.h"
1093 #include "../classes/coreb_2.h"
1094 #include "../classes/inta_2.h"
1095 #include "../classes/pxa_2.h"
1096 #include "../classes/wdb_2.h"
1097 #include "../classes/oca_2.h"
1098 #include "../classes/cta_2.h"
1099 #include "../classes/ctc_2.h"
1100 #include "../classes/ica_2.h"
1101 #include "../classes/occ_2.h"
1102 #include "../classes/ctd_2.h"
1103 #include "../classes/psa_2.h"
1104 #include "../classes/spia_2.h"
1105 #include "../classes/uarta_2.h"
1106 #include "../classes/twia_2.h"
1107 #include "../classes/aca_2.h"
1108 #include "../classes/adb_2.h"
1109 #include "../classes/eea_2.h"
1110 #include "../classes/fla_2.h"
1111 
1112 
1113 HW_INLINE void _hwa_setup_context( hwa_t *hwa )
1114 {
1115  _hwa_setup_r( shared, eimsk );
1116  _hwa_setup_r( shared, eifr );
1117  _hwa_setup_r( shared, eicr );
1118  _hwa_setup_r( shared, gtccr );
1119  _hwa_setup_r( shared, prr );
1120  _hwa_setup_r( shared, did1 );
1121  _hwa_setup_r( shared, did0 );
1122  _hwa_setup_r( shared, pcicr );
1123  _hwa_setup_r( shared, pcifr );
1124 
1125  _hwa_setup_o( core0 );
1126  _hwa_setup_o( portb );
1127  _hwa_setup_o( portc );
1128  _hwa_setup_o( portd );
1129  _hwa_setup_o( pcic0 );
1130  _hwa_setup_o( pcic1 );
1131  _hwa_setup_o( pcic2 );
1132  _hwa_setup_o( watchdog0 );
1133  _hwa_setup_o( counter0 );
1134  _hwa_setup_o( counter1 );
1135  _hwa_setup_o( counter2 );
1136 
1137  _hwa_setup_o( spi0 );
1138  _hwa_setup_o( uart0 );
1139  _hwa_setup_o( twi0 );
1140  _hwa_setup_o( acmp0 );
1141  _hwa_setup_o( adc0 );
1142 }
1143 
1144 
1145 HW_INLINE void _hwa_init_context( hwa_t *hwa )
1146 {
1147  _hwa_init_r( shared, eimsk, 0 );
1148  _hwa_init_r( shared, eifr, 0 );
1149  _hwa_init_r( shared, eicr, 0 );
1150  _hwa_init_r( shared, gtccr, 0 );
1151  _hwa_init_r( shared, prr, 0 );
1152  _hwa_init_r( shared, did1, 0 );
1153  _hwa_init_r( shared, did0, 0 );
1154  _hwa_init_r( shared, pcicr, 0 );
1155  _hwa_init_r( shared, pcifr, 0 );
1156 
1157  _hwa_init_o( core0 );
1158  _hwa_init_o( portb );
1159  _hwa_init_o( portc );
1160  _hwa_init_o( portd );
1161  _hwa_init_o( pcic0 );
1162  _hwa_init_o( pcic1 );
1163  _hwa_init_o( pcic2 );
1164  _hwa_init_o( watchdog0 );
1165  _hwa_init_o( counter0 );
1166  _hwa_init_o( counter1 );
1167  _hwa_init_o( counter2 );
1168  _hwa_init_o( spi0 );
1169  _hwa_init_o( uart0 );
1170  _hwa_init_o( twi0 );
1171  _hwa_init_o( acmp0 );
1172  _hwa_init_o( adc0 );
1173 }
1174 
1175 
1176 HW_INLINE void _hwa_commit_context( hwa_t *hwa )
1177 {
1178  _hwa_solve_o( counter0 );
1179  _hwa_solve_o( counter1 );
1180  _hwa_solve_o( counter2 );
1181 
1182  _hwa_commit_r( shared, eimsk );
1183  _hwa_commit_r( shared, eifr );
1184  _hwa_commit_r( shared, eicr );
1185  _hwa_commit_o( core0 );
1186  _hwa_commit_r( shared, prr );
1187  _hwa_commit_o( watchdog0 );
1188  _hwa_commit_o( portb );
1189  _hwa_commit_o( portc );
1190  _hwa_commit_o( portd );
1191  _hwa_commit_r( shared, pcifr );
1192  _hwa_commit_r( shared, pcicr );
1193  _hwa_commit_o( pcic0 );
1194  _hwa_commit_o( pcic1 );
1195  _hwa_commit_o( pcic2 );
1196 
1197  _hwa_commit_r( shared, gtccr );
1198  _hwa_commit_o( counter0 );
1199  _hwa_commit_o( counter1 );
1200  _hwa_commit_o( counter2 );
1201 
1202  _hwa_commit_o( spi0 );
1203  _hwa_commit_o( uart0 );
1204  _hwa_commit_o( twi0 );
1205  _hwa_commit_o( acmp0 );
1206  _hwa_commit_r( shared, did1 );
1207  _hwa_commit_o( adc0 );
1208  _hwa_commit_r( shared, did0 );
1209 }
1210 
1211 #endif /* !defined __ASSEMBLER__ */
_hwa_init_r
#define _hwa_init_r(o, r, v)
Initialize an HWA register of an object with its reset value.
Definition: hwa_2.h:369
_hwa_init_o
#define _hwa_init_o(o)
Initialize the HWA context registers of an object with their reset value.
Definition: hwa_2.h:331
_hwa_solve_o
#define _hwa_solve_o(o)
Solve the configuration of an object.
Definition: hwa_2.h:340
hwa
#define hwa(...)
hwa( action, object [,...] ) stores an action for an object into a HWA context.
Definition: hwa_macros.h:552
_hwa_setup_r
#define _hwa_setup_r(o, r)
Create a HWA register.
Definition: hwa_2.h:359
atmegax8_fuses.h
ATmegaX8 fuses & user definitions.
_hwa_commit_r
#define _hwa_commit_r(o, r)
Commit one object hardware register.
Definition: hwa_2.h:379
_hwa_commit_o
#define _hwa_commit_o(o)
Commit the registers of an object.
Definition: hwa_2.h:349
_hwa_setup_o
#define _hwa_setup_o(o)
Initialize the HWA context registers addresses of an object.
Definition: hwa_2.h:322